Graceful degradation in synthesis of VLSI ICs

Abstract

Increasing levels of societal reliance on computerized solutions demand fault-resilient solutions. At the same time, system-on-a-chip levels of integration, demand a reexamination and migration of traditional system level fault resilience techniques to the integrated circuit level. Automated synthesis methodologies need to provide embedded, low-cost fault resilience properties, capable of ensuring fault resilience for all on-chip components and interconnects. The outlined approaches in this paper pioneer the insertion of unabridged fault resilience properties at the IC level through highly automated approaches. The experimental results show cost-effective solutions, with no performance degradation, in the synthesized ASICs.