{"title":"Diagnosis of scan chain failures","authors":"Yuejian Wu","doi":"10.1109/DFTVS.1998.732169","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732169","url":null,"abstract":"This paper first analyzes faulty scan chain behaviors. In addition to stuck-at faults, we also consider timing faults due to hold time violations Test sequences to determine the fault types in a failing scan chain are presented. This is followed by a presentation of two scan design techniques that simplifies scan chain fault diagnosis for both stuck-at and timing faults.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123884933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Al-Khalili, S. Adham, C. Rozon, Moazzem Hossain, D. Racz
{"title":"Comprehensive defect analysis and defect coverage of CMOS circuits","authors":"D. Al-Khalili, S. Adham, C. Rozon, Moazzem Hossain, D. Racz","doi":"10.1109/DFTVS.1998.732154","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732154","url":null,"abstract":"In this paper we present a methodology to perform defect analysis of digital CMOS circuits using comprehensive transistor macro defect models. These models are based on eighteen defects, hard and soft, for each MOS transistor. Defects are activated individually and circuits are exhaustively simulated to determine the responses, which are then compared with that of gold circuits. Both defect and fault coverages are determined including statistics to determine the effectiveness of a testing method. Results on combined testing and implications on incremental fault coverages are presented.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126974638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Functional verification coverage vs. physical stuck-at fault coverage","authors":"Xiao Sun, Carmie Hull","doi":"10.1109/DFTVS.1998.732157","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732157","url":null,"abstract":"It is shown that a functional verification coverage model based on functional property model is a super set of nonredundant physical stuck-at faults in this paper. This paper overviews a methodology to validate and verify hardware or software systems where the specification is modeled as a finite functional property model. The methodology proposed can produce a short verification/test with short verification and test application time and high design verification/physical fault coverage.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133470176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Increasing current testing resolution","authors":"C. Thibeault","doi":"10.1109/DFTVS.1998.732159","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732159","url":null,"abstract":"The purpose of this paper is to experimentally show that I/sub DDQ/ testing has a rather poor resolution when used to estimate additional current caused by active defects, and that a significant current testing resolution can be obtained with simple data processing. We propose a methodology based on the use of two different criteria the two kinds of current defects-passive and active. This paper represents the first step and deals with active defects. Here we compare different methods applied to estimate additional current caused by this sort of defects. Using Sematech Project S121 data, we show that a resolution gain of 10 over I/sub DDQ/ testing can be reached with simple data processing.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"446 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116153793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On-chip test embedding for multi-weighted random LFSRs","authors":"D. Kagaris, S. Tragoudas, Amitava Majumdar","doi":"10.1109/DFTVS.1998.732160","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732160","url":null,"abstract":"We present for the first time a systematic approach for partitioning deterministic test set into subsets so that multiple weight-sets, one weight-set per subset, are generated for efficient Weighted Random LFSR Test Pattern Generation. The basic partitioning criterion is the maximum Hamming distance between any two test patterns in the same set. The number of test patterns within each subset is also taken into consideration. The proposed tools make use of optimal partitioning algorithms. Experimental results clearly indicate the effectiveness of the proposed scheme.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123186181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Chiusano, Fulvio Corno, M. Reorda, Roberto Vietti
{"title":"A system for evaluating on-line testability at the RT-level","authors":"S. Chiusano, Fulvio Corno, M. Reorda, Roberto Vietti","doi":"10.1109/DFTVS.1998.732177","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732177","url":null,"abstract":"This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an exploration of different testable architectures before committing to the final design. Circuits are modeled as finite state machines, and a set of transformations can be defined inside the system to account for different on-line test strategies. Preliminary experiments show that the information made available by the evaluation system can be used to drive the testable design process towards a better trade-off point.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130263664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Management of critical areas and defectivity data for yield trend modeling","authors":"S. Barberan, F. Duvivier","doi":"10.1109/DFTVS.1998.732147","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732147","url":null,"abstract":"This paper reports a yield model applied to a large set of defectivity data measured on a 0.35 micron process in ST Crolles plant and critical areas extracted by survey sampling. It takes into account all defect densities measured at the main process steps and determines their respective yield loss. The robustness of the model was tested week by week during three months of production for two high volume devices. The model was then applied wafer by wafer on a new process version.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130078365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Vogels, M. Dohmen, P. V. Duijvenboden, R. A. Latimer, J. Heffernan
{"title":"A yield improvement program using process control and process optimisation for particle reduction using in situ particle monitoring on a Semitool Magnum","authors":"L. Vogels, M. Dohmen, P. V. Duijvenboden, R. A. Latimer, J. Heffernan","doi":"10.1109/DFTVS.1998.732146","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732146","url":null,"abstract":"Semitool, HYT/Pacific Scientific and MOS4YOU/Philips Semiconductors decided to investigate in close co-operation the process control and process optimisation through particle reduction on a Semitool Magnum wet clean system, by use of an In Situ Particle Monitor (ISPM). This is a new application for ISPM, for Semitool and for Philips. The goal of the co-operation is to evaluate the ISPM, to interpret the data generated and to improve the overall performance of the wet clean system. The ISPM detected wafers which were not cleaned properly as well as wafers which were not properly dry etched in a previous production step. Furthermore, the ISPM allowed us to improve the cleaning process, by improving the cleaning cycle of the chemical. Hereby, the ISPM proved to be a valuable tool for process control and process improvement. As particles are the main source for yield loss, the impact of a particle reduction program on yield is straightforward.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126415640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FPGA design for decimeter scale integration (DMSI)","authors":"G. Chapman","doi":"10.1109/DFTVS.1998.732152","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732152","url":null,"abstract":"Creating large area FPGAs is limited by defective sections and the maximum reticule print size (/spl sim/3/spl times/3 cm). FPGAs are well suited for expanding into monolithic multiprint systems 2 to 9 times larger (5-10 cm square) we call deciMeter scale integration (DMSI). DMSI expands system capacity, while producing many copies per wafer. Its design criteria is much simpler than the complex wafer scale integration, but still uses defect avoidance routing around flawed blocks to build complete working systems. FPGAs have the main features required for successful DMSI systems: a repeatable cell, built in switchable flexible routing, high connectivity requirements between cell blocks, and flexibility with many potential applications. Modest changes at the periphery of FPGAs chips enables DMSI capability. Laser formed connections and cuts have proven effectiveness in bypassing fabrication time defects and creating defect free working wafer scale systems. The important DMSI criteria for laser defect avoidance is that defect free devices should need no correction. Depending on the DMSI size and current chip yields design defect avoidance requirements vary from simple row column substitution to cell by cell/row column substitution with redundant signal paths. Power shorts defects and how they are handled prove an important limitation on chip size.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126469001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Specification-driven test design for analog circuits","authors":"P. Variyam, A. Chatterjee","doi":"10.1109/DFTVS.1998.732183","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732183","url":null,"abstract":"In this paper we present a test generation approach for time and frequency domain testing of analog circuits. Tests are generated to detect faulty circuits which violate one or more circuit specifications without explicitly performing exhaustive specification based tests. We formulate the test stimulus generation problem as a search problem in which the primary goal is to reduce the probability of classifying a bad circuit as good and vice versa. Genetic algorithms are used to search for the optimum transient and steady state tests.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134462888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}