{"title":"功能验证覆盖率与物理故障覆盖率","authors":"Xiao Sun, Carmie Hull","doi":"10.1109/DFTVS.1998.732157","DOIUrl":null,"url":null,"abstract":"It is shown that a functional verification coverage model based on functional property model is a super set of nonredundant physical stuck-at faults in this paper. This paper overviews a methodology to validate and verify hardware or software systems where the specification is modeled as a finite functional property model. The methodology proposed can produce a short verification/test with short verification and test application time and high design verification/physical fault coverage.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Functional verification coverage vs. physical stuck-at fault coverage\",\"authors\":\"Xiao Sun, Carmie Hull\",\"doi\":\"10.1109/DFTVS.1998.732157\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"It is shown that a functional verification coverage model based on functional property model is a super set of nonredundant physical stuck-at faults in this paper. This paper overviews a methodology to validate and verify hardware or software systems where the specification is modeled as a finite functional property model. The methodology proposed can produce a short verification/test with short verification and test application time and high design verification/physical fault coverage.\",\"PeriodicalId\":245879,\"journal\":{\"name\":\"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-11-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1998.732157\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1998.732157","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Functional verification coverage vs. physical stuck-at fault coverage
It is shown that a functional verification coverage model based on functional property model is a super set of nonredundant physical stuck-at faults in this paper. This paper overviews a methodology to validate and verify hardware or software systems where the specification is modeled as a finite functional property model. The methodology proposed can produce a short verification/test with short verification and test application time and high design verification/physical fault coverage.