Comprehensive defect analysis and defect coverage of CMOS circuits

Abstract

In this paper we present a methodology to perform defect analysis of digital CMOS circuits using comprehensive transistor macro defect models. These models are based on eighteen defects, hard and soft, for each MOS transistor. Defects are activated individually and circuits are exhaustively simulated to determine the responses, which are then compared with that of gold circuits. Both defect and fault coverages are determined including statistics to determine the effectiveness of a testing method. Results on combined testing and implications on incremental fault coverages are presented.