内插式快闪ADC中非理想性的多级线性建模提高良率

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI:10.1109/DFTVS.1998.732182

A. Boni, A. Pierazzi

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引用次数: 1

摘要

本文讨论了一种基于多级线性模型的内插式闪存a /D转换器诊断技术。它允许在第一块硅中识别非理想来源，例如布局缺陷或热梯度，并为通过布局改进提高良率提供指导，从而优于通常不考虑布局相关问题的蒙特卡罗技术。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Yield enhancement by multi-level linear modeling of non-idealities in an interpolated flash ADC

The paper discusses a diagnostic technique for interpolated flash A/D converters based on a multi-level linear model. It allows identification of non-ideality sources, such as layout imperfections or thermal gradients, in the first silicon and provides guidance for the improvement of yield by layout refinement, thus outperforming Monte Carlo techniques which do not usually account for layout-related issues.

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Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)

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