Orphan metal removal as an element of DFM

Abstract

Discussion of improving the yield and manufacturability of designs through the modification of metal tracks has apparently neglected a potentially important first step-that of removal of metal which is surplus to the design. A technique is described for the identification and removal of surplus or 'orphan' metal using tools present in the Cadence layout system. Application of this technique to a semi-custom product designed in a 0.8 micron analog BiCMOS process is outlined.