{"title":"残金属去除是DFM的一个元素","authors":"Neil Harrison","doi":"10.1109/DFTVS.1998.732149","DOIUrl":null,"url":null,"abstract":"Discussion of improving the yield and manufacturability of designs through the modification of metal tracks has apparently neglected a potentially important first step-that of removal of metal which is surplus to the design. A technique is described for the identification and removal of surplus or 'orphan' metal using tools present in the Cadence layout system. Application of this technique to a semi-custom product designed in a 0.8 micron analog BiCMOS process is outlined.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Orphan metal removal as an element of DFM\",\"authors\":\"Neil Harrison\",\"doi\":\"10.1109/DFTVS.1998.732149\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Discussion of improving the yield and manufacturability of designs through the modification of metal tracks has apparently neglected a potentially important first step-that of removal of metal which is surplus to the design. A technique is described for the identification and removal of surplus or 'orphan' metal using tools present in the Cadence layout system. Application of this technique to a semi-custom product designed in a 0.8 micron analog BiCMOS process is outlined.\",\"PeriodicalId\":245879,\"journal\":{\"name\":\"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-11-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1998.732149\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1998.732149","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Discussion of improving the yield and manufacturability of designs through the modification of metal tracks has apparently neglected a potentially important first step-that of removal of metal which is surplus to the design. A technique is described for the identification and removal of surplus or 'orphan' metal using tools present in the Cadence layout system. Application of this technique to a semi-custom product designed in a 0.8 micron analog BiCMOS process is outlined.