Semiconductor Science and Technology最新文献_第5页

The impacts of SiO2 atomic-layer-deposited passivation layer thickness on GaN-based green micro-LEDs 二氧化硅原子层沉积钝化层厚度对氮化镓基绿色微型发光二极管的影响

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-02-28 DOI: 10.1088/1361-6641/ad2b0a

Youcai Deng, Jinlan Chen, Saijun Li, He Huang, Zhong Liu, Zijun Yan, Shouqiang Lai, Lijie Zheng, Tianzhi Yang, Zhong Chen, Tingzhu Wu

{"title":"The impacts of SiO2 atomic-layer-deposited passivation layer thickness on GaN-based green micro-LEDs","authors":"Youcai Deng, Jinlan Chen, Saijun Li, He Huang, Zhong Liu, Zijun Yan, Shouqiang Lai, Lijie Zheng, Tianzhi Yang, Zhong Chen, Tingzhu Wu","doi":"10.1088/1361-6641/ad2b0a","DOIUrl":"https://doi.org/10.1088/1361-6641/ad2b0a","url":null,"abstract":"In this study, we fabricated 76 × 127 <italic toggle=\"yes\">µ</italic>m2 green GaN-based micro-light-emitting-diodes (micro-LEDs) with atomic-layer-deposited (ALD) SiO2 passivation layers whose thicknesses were 0, 15, and 100 nm. The optoelectrical and communication performances of these devices were measured and analysed. The current-voltage results showed that ALD technology reduced the leakage current and enhanced the forward current of micro-LEDs. Compared with those of micro-LEDs without the passivation layer, the external quantum efficiency of micro-LEDs with 15 and 100 nm-thick SiO2 passivation layers increased by 23.64% and 19.47%, respectively. Furthermore, analysis of the EQE of the samples at room temperature using the ABC + <italic toggle=\"yes\">f</italic>(n) model revealed the differences in the physical mechanisms of green micro-LEDs. Moreover, the communication performance indicated that ALD sidewall passivation reduced the carrier lifetime and improved the communication performance of green micro-LEDs.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"17 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140005779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

TMD material investigation for a low hysteresis vdW NCFET logic transistor 用于低磁滞 vdW NCFET 逻辑晶体管的 TMD 材料研究

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-02-28 DOI: 10.1088/1361-6641/ad2b09

I Blessing Meshach Dason, N Kasthuri, D Nirmal

{"title":"TMD material investigation for a low hysteresis vdW NCFET logic transistor","authors":"I Blessing Meshach Dason, N Kasthuri, D Nirmal","doi":"10.1088/1361-6641/ad2b09","DOIUrl":"https://doi.org/10.1088/1361-6641/ad2b09","url":null,"abstract":"Boltzmann limit is inevitable in conventional MOSFETs, which prevent them to be used for low-power applications. Research in device physics can address this problem by selection of proper materials satisfying our requirements. Recently, 2D transition metal di-chalcogenide (TMD) materials are gaining interest because they help alleviate short-channel effects and DIBL problems. The TMD materials are composed by covalently bonded weak van der Waals (vdW) interaction and can be realized as hetero structures with 2D ferro-electric material CuInP2S6 at the gate stack. This paper demonstrates a vdW negative capacitance field effect transistor (NCFET) structure in TCAD and the design was validated for voltage-current Characteristics. Parametric analysis shows MoS2 with phenomenal on/off ratio, narrow hysteresis than the counterparts. Simulation shows that MoS2 vdW NCFET has a high transconductance of 2.36 <italic toggle=\"yes\">µ</italic>S <italic toggle=\"yes\">µ</italic>m−1. A steep slope of 28.54 mV dec−1 is seen in MoS2 vdW NCFET which promises the performance of logic applications at a reduced supply voltage.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"124 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140011074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Deep-ultraviolet LEDs with an Al-graded p-AlGaN layer exhibiting high wall-plug efficiency and high modulation bandwidth simultaneously 同时具有高壁插效率和高调制带宽的铝梯度对铝镓氮层深紫外发光二极管

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-02-16 DOI: 10.1088/1361-6641/ad238b

Bingyue Cui, Jie Yang, Xingfa Gao, Jiaheng He, Zhe Liu, Zhe Cheng, Yun Zhang

引用次数: 0

Polarization-doped n-p-i-p-n GaN-based parallel phototransistor with thick GaN absorption layer for achieving high responsivity 具有厚氮化镓吸收层的偏振掺杂 n-p-i-p-n 氮化镓基并联光电晶体管，可实现高响应率

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-02-08 DOI: 10.1088/1361-6641/ad2427

Zhengji Zhu, Chunshuang Chu, Kangkai Tian, Zhan Xuan, Zhiwei Xie, Ke Jiang, Yonghui Zhang, Xiaojuan Sun, Zi-Hui Zhang, Dabing Li

引用次数: 0

Integrated 2T1C pixel circuit with a-Si TFT and NMOS for active matrix mini-LED displays 集成 2T1C 像素电路，采用 a-Si TFT 和 NMOS，用于有源矩阵微型 LED 显示器

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-02-07 DOI: 10.1088/1361-6641/ad238c

Chenming Zhong, Guangyao Li, Xi Zheng, Lihong Zhu, Jianbang Zhuang, Yijun Lu, Zhong Chen, Weijie Guo

引用次数: 0

Design and simulation of high performance β-Ga2O3 super barrier rectifier with a current blocking layer 带电流阻断层的高性能 β-Ga2O3 超级势垒整流器的设计与仿真

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-01-18 DOI: 10.1088/1361-6641/ad1ccb

Zhenghua Wang, Lei Yuan, Bo Peng, Xinming Xie, Yuming Zhang, Renxu Jia

{"title":"Design and simulation of high performance β-Ga2O3 super barrier rectifier with a current blocking layer","authors":"Zhenghua Wang, Lei Yuan, Bo Peng, Xinming Xie, Yuming Zhang, Renxu Jia","doi":"10.1088/1361-6641/ad1ccb","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1ccb","url":null,"abstract":"In this work, a <italic toggle=\"yes\">β</italic>-Ga2O3 super barrier rectifier with a current blocking layer (CSBR) is proposed. Its static characteristics, dynamic characteristics and surge capability are investigated by TCAD simulation. The Baliga’s figure of merit (BFOM) can reach 1.62 GW cm−2 with the on-resistance of 3.68 mΩ cm−2 and the breakdown voltage of 2447 V, exhibiting excellent performance. Foremost, the turn-on and turn-off of the device is controlled by metal-oxide-semiconductor (MOS) structure. The reverse recovery time is 11.2 ns, which is compatible with that of a Schottky diode. Simulation results show that the dimensions of the cells and the proportion of the ohmic contact region in the cells are the key parameters affecting the reverse recovery time. In addition, the CSBR with double-side cooling configuration demonstrates high surge capability. It can sustain a peak surge current density of 5000 A cm−2, which is more than 10 times its forward current (<italic toggle=\"yes\">V</italic>\u0000Forward = 3.0 V). Overall, the proposed structure has a high BFOM, excellent reverse characteristics and high reliability, demonstrating its potential in high voltage applications. Moreover, CSBR can be embedded into Ga2O3-MOSFET as a free-wheeling diode.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"26 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139510086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Terahertz dielectric properties of Fe3O4 thin ﬁlms deposited on Si (100) substrate 沉积在硅（100）衬底上的 Fe3O4 薄膜的太赫兹介电性能

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-01-09 DOI: 10.1088/1361-6641/ad1cca

Ashish Khandelwal, L. S. Sharath Chandra, Shilpam Sharma, A. Sagdeo, Ram Janay Choudhary, M. K. Chattopadhyay

引用次数: 0

A novel split gate trench MOSFET with high-k pillar embedded for higher breakdown voltage 嵌入高 K 柱的新型分裂栅沟槽 MOSFET，可实现更高的击穿电压

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-01-09 DOI: 10.1088/1361-6641/ad1c62

Li Huang, Xiaojin Li, Yabin Sun, Yanling Shi

引用次数: 0

Impact of CdSeTe and CdSe film deposition parameter on the properties of CdSeTe/CdTe absorber structure for solar cell applications 碲化镉和硒化镉薄膜沉积参数对用于太阳能电池的碲化镉/硒化镉吸收体结构性能的影响

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-01-08 DOI: 10.1088/1361-6641/ad1c4d

A. Çiriş, Y. Atasoy, M. Tomakin, Abdullah Karaca, T. Küçükömeroğlu, E. Bacaksız

{"title":"Impact of CdSeTe and CdSe film deposition parameter on the properties of CdSeTe/CdTe absorber structure for solar cell applications","authors":"A. Çiriş, Y. Atasoy, M. Tomakin, Abdullah Karaca, T. Küçükömeroğlu, E. Bacaksız","doi":"10.1088/1361-6641/ad1c4d","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1c4d","url":null,"abstract":"\u0000 In this study, the effect of depositing CdSeTe and CdTe layers at different substrate temperatures by evaporation in vacuum on the properties of the CdSeTe/CdTe stacks was investigated. First, CdSeTe layers in stack structure were grown at substrate temperatures of 150, 200 and 250°C and then CdTe layers on the CdSeTe produced with the optimum temperature were coated at substrate temperatures of 150, 200 and 250°C. The employing of substrate temperatures up to 150°C on both CdSeTe and CdTe films in CdSeTe/CdTe stacks demonstrated the presence of Te and/or oxide phases as well as the alloying, while more stable phase structures at higher temperatures. In the CdSeTe/CdTe stack, the increase in substrate temperature of CdSeTe promoted the alloying, while it weakened the alloy in which was applied in CdTe. It was concluded that under the applied experimental conditions, substrate temperatures of 250°C and 200°C with the graded alloying structure, suitable absorption sites, more homogeneous surface morphology for potential solar cell applications would be more suitable for CdSeTe and CdTe, respectively. As a result, the application of substrate temperature to CdSeTe or CdTe in the stacks can be used as a tool to control the properties of the stack structure.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"50 14","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139447189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multiple factors of regulation for transient negative capacitance in PbZr(1-x)Ti(x)O3 ferroelectric thin films PbZr(1-x)Ti(x)O3 铁电薄膜瞬态负电容的多种调节因素

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-01-05 DOI: 10.1088/1361-6641/ad1ba8

Hai-Ze Cao, Y. G. Xiao, Ning-Jie Ma, Li-Sha Yang, Yong Jiang, K. Xiong, Gang Li, Jun OuYang, Minghua Tang

{"title":"Multiple factors of regulation for transient negative capacitance in PbZr(1-x)Ti(x)O3 ferroelectric thin films","authors":"Hai-Ze Cao, Y. G. Xiao, Ning-Jie Ma, Li-Sha Yang, Yong Jiang, K. Xiong, Gang Li, Jun OuYang, Minghua Tang","doi":"10.1088/1361-6641/ad1ba8","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1ba8","url":null,"abstract":"\u0000 The negative capacitance (NC) of ferroelectric materials can effectively break the “Boltzmann tyranny” and drive the continuation scaling of Moore’s law. In this work, to find a novel way of amplifying the transient NC, a series network of external resistors and PbZr(1-x)Ti(x)O3 (PZT) ferroelectric capacitors were constructed. Uniform modeling and simulation were performed using Kirchhoff’s current law, electrostatics equations, and Landau-Khalatnikov equations. The derived results revealed that the mismatch of switching rate between free charge and polarization during ferroelectric domain switching is responsible for the transient NC generation. Some interesting results were obtained for the regulation of the transient NC by various factors such as the strain between the ferroelectric film and substrate, the viscosity coefficient, the ratio of Ti components, the external resistance magnitude, and the operating temperature. This work provides considerable insight into the control of ferroelectric transient NC, and offers guidance for obtaining larger and longer transient NC in the widely used PZT thin films.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"19 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139383708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0