Semiconductor Science and Technology最新文献

{"title":"Impact of CdSeTe and CdSe film deposition parameter on the properties of CdSeTe/CdTe absorber structure for solar cell applications","authors":"A. Çiriş, Y. Atasoy, M. Tomakin, Abdullah Karaca, T. Küçükömeroğlu, E. Bacaksız","doi":"10.1088/1361-6641/ad1c4d","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1c4d","url":null,"abstract":"\u0000 In this study, the effect of depositing CdSeTe and CdTe layers at different substrate temperatures by evaporation in vacuum on the properties of the CdSeTe/CdTe stacks was investigated. First, CdSeTe layers in stack structure were grown at substrate temperatures of 150, 200 and 250°C and then CdTe layers on the CdSeTe produced with the optimum temperature were coated at substrate temperatures of 150, 200 and 250°C. The employing of substrate temperatures up to 150°C on both CdSeTe and CdTe films in CdSeTe/CdTe stacks demonstrated the presence of Te and/or oxide phases as well as the alloying, while more stable phase structures at higher temperatures. In the CdSeTe/CdTe stack, the increase in substrate temperature of CdSeTe promoted the alloying, while it weakened the alloy in which was applied in CdTe. It was concluded that under the applied experimental conditions, substrate temperatures of 250°C and 200°C with the graded alloying structure, suitable absorption sites, more homogeneous surface morphology for potential solar cell applications would be more suitable for CdSeTe and CdTe, respectively. As a result, the application of substrate temperature to CdSeTe or CdTe in the stacks can be used as a tool to control the properties of the stack structure.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"50 14","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139447189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multiple factors of regulation for transient negative capacitance in PbZr(1-x)Ti(x)O3 ferroelectric thin films","authors":"Hai-Ze Cao, Y. G. Xiao, Ning-Jie Ma, Li-Sha Yang, Yong Jiang, K. Xiong, Gang Li, Jun OuYang, Minghua Tang","doi":"10.1088/1361-6641/ad1ba8","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1ba8","url":null,"abstract":"\u0000 The negative capacitance (NC) of ferroelectric materials can effectively break the “Boltzmann tyranny” and drive the continuation scaling of Moore’s law. In this work, to find a novel way of amplifying the transient NC, a series network of external resistors and PbZr(1-x)Ti(x)O3 (PZT) ferroelectric capacitors were constructed. Uniform modeling and simulation were performed using Kirchhoff’s current law, electrostatics equations, and Landau-Khalatnikov equations. The derived results revealed that the mismatch of switching rate between free charge and polarization during ferroelectric domain switching is responsible for the transient NC generation. Some interesting results were obtained for the regulation of the transient NC by various factors such as the strain between the ferroelectric film and substrate, the viscosity coefficient, the ratio of Ti components, the external resistance magnitude, and the operating temperature. This work provides considerable insight into the control of ferroelectric transient NC, and offers guidance for obtaining larger and longer transient NC in the widely used PZT thin films.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"19 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139383708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bi-directional threshold voltage shift of amorphous InGaZnO thin film transistors under alternating bias stress","authors":"Hyunjin Kim, Beom Jung Kim, Jungyeop Oh, Sung-Yool Choi, Hamin Park","doi":"10.1088/1361-6641/ad1b15","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b15","url":null,"abstract":"\u0000 Amorphous InGaZnO (a-IGZO) has attracted a lot of attention as a high-mobility channel material for thin film transistors (TFTs). However, the instability mechanism involving threshold voltage and subthreshold swing in a-IGZO TFTs still requires further investigation. In this study, we investigated the electrical instability of amorphous InGaZnO thin film transistors subjected to alternating positive and negative bias stresses. Based on the respective mechanisms under positive and negative bias stresses, including ionization and spatial movement of oxygen vacancies, bi-directional threshold voltage shifts were observed under alternating bias stress. The subthreshold swing values vary with the bias stress polarity, reflecting the presence and distribution of oxygen vacancies. Our findings reveal a complementary mechanism based on oxygen vacancies, elucidating the behavior under complex bias stress schemes and extending our understanding of instability mechanisms beyond monotonous bias stress.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"24 11","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139384510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-resistive gate module for RF GaN-HFETs by electroplating","authors":"Hossein Yazdani, Andreas Thies, Paul Stützle, O. Bengtsson, Oliver Hilt, Wolfgang Heinrich, Joachim Wuerfl","doi":"10.1088/1361-6641/ad1b16","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b16","url":null,"abstract":"\u0000 This paper presents a novel approach for reducing the gate resistance (Rg) of K and Ka-band GaN HFETs with 150 nm gate length through a new gate metallization technique. The method involves increasing the gate cross-section via galvanic metallization using FBH's Ir-sputter gate technology, which allows an increase in gate metal thickness from the current 0.4 μm to approximately 1.0 μm for the transistors under investigation. This optimization leads to a substantial 50% reduction in gate series resistance, resulting in significant improvements in the RF performance. Specifically, the devices achieve 20% higher output power density and 10% better power-added efficiency (PAE) at 20 GHz and Vds = 20 V. The decreased gate resistance enables new degrees of freedom in design, such as longer gate fingers and/or shorter gate lengths, for more efficient power cells operating in this frequency range.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"28 5","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139384456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel low trigger voltage low leakage SCR for low-voltage ESD protection","authors":"Jizhi Liu, FEILONG YANG, YILIN LIU","doi":"10.1088/1361-6641/ad1b14","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b14","url":null,"abstract":"\u0000 Reducing trigger voltage has always been a research hotspot in low-voltage electrostatic discharge (ESD) protection applications for integrated circuit. Thus, a novel low trigger voltage low leakage silicon-controlled rectifier (LTVLLSCR) for low-voltage ESD protection has been proposed. The proposed device uses a PMOS connected with the SCR to reduce the trigger voltage and the PMOS gate can be applied with the supply voltage to further reduce the trigger voltage and the leakage current. The operating principle and the physical mechanism of the proposed device were discussed by the Human Body Model simulation. The ESD characteristics of the proposed device were verified in 55 nm CMOS process. The experimental results demonstrate that the trigger voltage of the proposed device can reach a minimum of 2.86 V with an external bias, and the leakage current at 25 ℃ is about 1 nA which can be reduced by 13% with an external bias. With lower trigger voltage, lower leakage, smaller ESD design window and good ESD robustness, the LTVLLSCR is very suitable for 1 V low voltage applications.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"2 15","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139386036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dual-directional SCR device with dual-gate controlled mechanism for ESD protection in photoelectric chip","authors":"Yujie Liu, Yang Wang, Jian Yang, Xiangliang Jin","doi":"10.1088/1361-6641/ad1b18","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b18","url":null,"abstract":"\u0000 The dual-directional silicon-controlled rectifier (DDSCR) is an electrostatic discharge (ESD) protection device. It can provide positive and negative ESD surge paths and has excellent robustness. However, industry-level sensors operating in strong electromagnetic interference environments impose higher reliability requirements on photoelectric chips. This paper proposed a novel DDSCR with a dual-gate controlled mechanism. By incorporating the gate diode triggering and the gate field modulation mechanism into the traditional DDSCR, and further utilizing additional parasitic PNP transistors for diversion, the proposed device exhibits significantly improved ESD characteristics. Measurement results indicate that, compared to DDSCR, the proposed device exhibits a 27.5% reduction in trigger voltage (Vt1), a 96.1% improvement in holding voltage (Vh), and achieves an equivalent Human Body Model (HBM) protection level of 11.45 kV, demonstrating exceptional design area efficiency. The experimental findings validate the effectiveness of the proposed device in 5 V photoelectric chip applications.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"56 9","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139386013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Oxygen reduction through specific surface area control of AlN powder for AlN single-crystal growth by physical vapor transport","authors":"ZeRen Wang, Xing-Yu Zhu, Qi-Yue Zhao, Jie-Jun Wu, Tongjun Yu","doi":"10.1088/1361-6641/ad1b13","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b13","url":null,"abstract":"\u0000 In the physical vapor transport (PVT) growth of AlN, re-oxidation of aluminum nitride (AlN) source powder happening in the process of setting seed crystal into crucible seems to be unavoidable. This process introduces oxygen just before AlN growth and has a significant impact on the crystal quality. In this paper, a high and low-temperature alternative sintering method (HLAS) is proposed based on the idea of specific surface area control to reduce the re-oxidation of AlN source powder. This method introduces cyclic sintering between 1500°C and 1900°C to the conventional three-step treatment repeatedly, which utilizes possible phase-transition along with the processes of powder sintering back and forth to increase the particle size and decrease the specific surface area significantly. The SEM (Scanning electron microscope) and BET (Brunauer, Emmett, and Teller) results showed that the specific surface area of AlN powder treated with the HLAS method can be reduced to one-third of that with the conventional method. Thus, the SIMS (secondary ion mass spectrometry) confirmed the reduction of oxygen impurity in AlN single-crystals to a good level of 1.5×1017cm-3. It is clear that this HLAS process is an effective way of controlling the specific surface area of AlN source powder, which contributes to the suppression of oxygen influence on PVT-AlN growth.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"68 40","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139385438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Phase transformation on HZO ferroelectric layer in ferroelectric random-access memory induced by x-ray irradiation","authors":"Chung-Wei Wu, Po-Hsun Chen, Ting-Chang Chang, Yung-Fang Tan, Shih-Kai Lin, Yu-Hsuan Yeh, Yong-Ci Zhang, Hsin-Ni Lin, Kai-Chun Chang, Chien-Hung Yeh, Simon Sze","doi":"10.1088/1361-6641/ad1130","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1130","url":null,"abstract":"In this study, electrical measurements on ferroelectric random-access memory by prior x-ray irradiation are conducted. Compared with an unirradiated device, parameters such as current leakage and remnant polarization of the irradiated device were unexpectedly improved. Besides, better reliabilities including the number of endurance times and retention time have also been demonstrated. To clarify the underlying physical mechanism, the electrical properties are analyzed. The current–voltage curve (<italic toggle=\"yes\">I–V</italic>) implies a change in the grain size in the ferroelectric layer (FL), and the capacitance–voltage curve (<italic toggle=\"yes\">C</italic>–<italic toggle=\"yes\">V</italic>) profile indicates that the FL undergoes a phase change during irradiation. Finally, according to the electrical results, a physical model is proposed as an explanation.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"19 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139102141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Strain engineering and strain measurement by spring tethers on suspended epitaxial GaN-on-Si photonic crystal devices","authors":"Jun Wang, R. Houdré","doi":"10.1088/1361-6641/ad1b17","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b17","url":null,"abstract":"\u0000 Suspended epitaxial gallium nitride (GaN) on silicon (Si) photonic crystal (PhC) devices suffer from large residual tensile strain, especially for long waveguides, because fine structures tend to crack due to large stress. By introducing spring-like tethers, designed by the combination of a spring network model and finite element method (FEM) simulations, the stress at critical locations was mitigated and the cracking issue was solved. Meanwhile, the tethered-beam structure was found to be potentially a powerful method for high-precision strain measurement in tensile thin films, and in this case, a strain of $2.27(pm0.01)times10^{-3}$ was measured in 350 nm epitaxial GaN-on-Si.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"61 9","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139386252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel 650 V snapback-free PMOS-RC-SJBT with low switching and reverse recovery losses","authors":"Yuanzhen Yang, Luping Li, Zehong Li, Qianshen Rao, Peng Chen, Min Ren","doi":"10.1088/1361-6641/ad112f","DOIUrl":"https://doi.org/10.1088/1361-6641/ad112f","url":null,"abstract":"A novel 650 V Snapback-free Reverse-conducting Super-junction (SJ) insulated gate bipolar transistor (RC-SJBT) with low switching and reverse recovery loss is proposed and investigated in paper. In where, SJ pillar acts as the drift region, meanwhile PMOS and Schottky are combined on the cathode side. Under the action of SJ pillar, the snapback is effectively suppressed and <inline-formula>\u0000<tex-math><?CDATA $V_{mathrm{on}}$?></tex-math>\u0000<mml:math overflow=\"scroll\"><mml:msub><mml:mi>V</mml:mi><mml:mrow><mml:mrow><mml:mi mathvariant=\"normal\">o</mml:mi><mml:mi mathvariant=\"normal\">n</mml:mi></mml:mrow></mml:mrow></mml:msub></mml:math>\u0000<inline-graphic xlink:href=\"sstad112fieqn1.gif\" xlink:type=\"simple\"></inline-graphic>\u0000</inline-formula>−<inline-formula>\u0000<tex-math><?CDATA $E_{mathrm{off}}$?></tex-math>\u0000<mml:math overflow=\"scroll\"><mml:msub><mml:mi>E</mml:mi><mml:mrow><mml:mrow><mml:mi mathvariant=\"normal\">o</mml:mi><mml:mi mathvariant=\"normal\">f</mml:mi><mml:mi mathvariant=\"normal\">f</mml:mi></mml:mrow></mml:mrow></mml:msub></mml:math>\u0000<inline-graphic xlink:href=\"sstad112fieqn2.gif\" xlink:type=\"simple\"></inline-graphic>\u0000</inline-formula> trade-off of IGBT is also improved. The PMOS and Schottky combined structure enhances on-state carriers of IGBT meanwhile reduces hole injection efficiency during reverse recovery of freewheel diode, thus the reverse recovery switching loss (<inline-formula>\u0000<tex-math><?CDATA $E_{mathrm{rec}}$?></tex-math>\u0000<mml:math overflow=\"scroll\"><mml:msub><mml:mi>E</mml:mi><mml:mrow><mml:mrow><mml:mi mathvariant=\"normal\">r</mml:mi><mml:mi mathvariant=\"normal\">e</mml:mi><mml:mi mathvariant=\"normal\">c</mml:mi></mml:mrow></mml:mrow></mml:msub></mml:math>\u0000<inline-graphic xlink:href=\"sstad112fieqn3.gif\" xlink:type=\"simple\"></inline-graphic>\u0000</inline-formula>) of PMOS-RC-SJBT is reduced without sacrificing IGBT’s performance. Investigated by the TCAD tools, the total switching loss of PMOS-RC-SJBT is reduced by 51.2% from Con. RC-IGBT and 40.6% than the latest commercial RC-IGBT IKWH30N65WR6 of Infineon. Besides that, <inline-formula>\u0000<tex-math><?CDATA $t_{mathrm{sc}}$?></tex-math>\u0000<mml:math overflow=\"scroll\"><mml:msub><mml:mi>t</mml:mi><mml:mrow><mml:mrow><mml:mi mathvariant=\"normal\">s</mml:mi><mml:mi mathvariant=\"normal\">c</mml:mi></mml:mrow></mml:mrow></mml:msub></mml:math>\u0000<inline-graphic xlink:href=\"sstad112fieqn4.gif\" xlink:type=\"simple\"></inline-graphic>\u0000</inline-formula> is increased by 35.3% than RC-SJBT. Additionally, the snapback-free P-collector width is reduced from 340 <italic toggle=\"yes\">µ</italic>m of Con.RC-IGBT to 40 <italic toggle=\"yes\">µ</italic>m of PMOS-RC-SJBT, where the current uniformity is substantially improved.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"71 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2023-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139053840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}