Semiconductor Science and Technology最新文献_第2页

Investigations into the robustness of the peak turn-on current slope method for junction temperature sensing in p-GaN HEMTs 对用于 p-GaN HEMT 结温检测的峰值导通电流斜率法稳健性的研究

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-08-27 DOI: 10.1088/1361-6641/ad68a0

Weihao Lu, Sheng Li, Ran Ye, Weixiong Mao, Zikang Zhang, Yanfeng Ma, Mingfei Li, Jiaxing Wei, Long Zhang, Jie Ma, Siyang Liu, Weifeng Sun

{"title":"Investigations into the robustness of the peak turn-on current slope method for junction temperature sensing in p-GaN HEMTs","authors":"Weihao Lu, Sheng Li, Ran Ye, Weixiong Mao, Zikang Zhang, Yanfeng Ma, Mingfei Li, Jiaxing Wei, Long Zhang, Jie Ma, Siyang Liu, Weifeng Sun","doi":"10.1088/1361-6641/ad68a0","DOIUrl":"https://doi.org/10.1088/1361-6641/ad68a0","url":null,"abstract":"In this paper, the robustness of a junction temperature sensing method using the peak of the turn-on current slope for enhanced p-GaN high-electron-mobility transistors is investigated in detail. With the help of a repetitive hard-switching test platform, compared to other temperature-sensitive electrical parameters, it is found that the maximum slope of the flowing current at the turn-on transition shows no trend in degradation, regardless of the applied switching stress. This parameter decreases solely with the increase in junction temperature, showing excellent temperature-dependent linearity. Furthermore, the applicability of this method to the detection of junction temperature under different external gate resistances and drain voltages is verified. The sensed junction temperatures are carried over to calculate the thermal resistance, which is also extracted by advanced thermal characterization test equipment as a reference. Therefore, based on the versatility, convenience and accuracy, the peak of the rising drain current slope has been proven to be the preferred alternative in system applications to detect junction temperatures.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"19 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Vertically aligned 2D tin sulfide (SnS) nanoplates for selective detection of ethanol gas at room temperature 垂直排列的二维硫化锡 (SnS) 纳米板用于室温下乙醇气体的选择性检测

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-08-27 DOI: 10.1088/1361-6641/ad6eaf

Hemant K Arora, Nikita Jain, Sunil Kumar, Nitin K Puri

{"title":"Vertically aligned 2D tin sulfide (SnS) nanoplates for selective detection of ethanol gas at room temperature","authors":"Hemant K Arora, Nikita Jain, Sunil Kumar, Nitin K Puri","doi":"10.1088/1361-6641/ad6eaf","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6eaf","url":null,"abstract":"Detection of ethanol gas quickly and efficiently at room temperature is crucial for ensuring environmental, human as well as industrial safety. In this work, we have demonstrated a chemiresistive room temperature ethanol gas sensor based on vertically aligned tin sulfide (SnS) nanoplates. X-ray diffraction (XRD), field-emission scanning electron microscopy (FESEM), and Brunauer–Emmett–Teller (BET) analysis have revealed the formation of orthorhombic, vertically aligned SnS nanoplates with high specific surface area. The sensor has been fabricated by depositing the SnS powder sample on ITO sheets using electrophoretic deposition (EPD), followed by the deposition of silver (Ag) electrodes using the thermal evaporation technique. The sensor obtained has exhibited a response value (<italic toggle=\"yes\">R</italic>g/<italic toggle=\"yes\">R</italic>a) of 17.4–400 ppm ethanol gas concentration, a quick response, and a recovery time of 12.4 s and 20.2 s at room temperature. The sensor has demonstrated long-term stability of 15 min, impressive selectivity, and remarkable repeatability across three successive test cycles of ethanol gas at 400 ppm. Based on the experimental sensing results, a plausible mechanism has been proposed for the sensor. The sensing response of SnS-based sensor at room temperature expands its potential for innovative applications across industries, marking a significant advancement in sensing technology.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"3 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology 采用 22 纳米技术的过剩-1 FinFET 电路的高效单级进位选择加法器

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-08-22 DOI: 10.1088/1361-6641/ad6e15

Jeevan Battini, Sivani Kosaraju

{"title":"An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology","authors":"Jeevan Battini, Sivani Kosaraju","doi":"10.1088/1361-6641/ad6e15","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6e15","url":null,"abstract":"Conventional carry select adders (CCSA) have two stages and are followed by multiplexers. CCSAs use ripple carry adders at two stages, which will introduce much delay due to carry propagation. To choose the option between an excess-1 result and a normal result, the CCSA employs a multiplexer. The proposed single-stage carry select adder (SSCSA) has a single stage and uses a new block to generate a normal and excess-1 result based on the readily available inputs (A and B). A novel architecture is developed and specifically designed to improve power dissipation and latency. It relies on a single circuit that produces normal/excess-1 results dependent on input carry. Heterogeneous logic combining CMOS, Dual Value Logic, and Transmission Gate Logic with 22 nm Fin-FETs powers the 1-bit SSCSA circuit. Better circuit regularity is displayed by the 4-bit SSCSA, as it only uses one type of 1-bit SSCSA. With the use of Cadence Virtuoso, ADEL, and ADEXL at 22 nm FinFET technology, all adders, including 4- and 8-bit adders, are designed, simulated, and examined. According to the resulting study, the 4-bit SSCSA outperforms the best adder among existing adders in terms of speed performance and power dissipation by 17.6% and 27.6%, respectively. By comparison with all other designs, SSCSAs outperform them at every corner.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"726 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel dual-gate negative capacitance TFET for highly sensitive label free biosensing 用于高灵敏无标记生物传感的新型双栅负电容 TFET

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-08-22 DOI: 10.1088/1361-6641/ad6eb0

Ravindra Kumar Maurya, Radhe Gobinda Debnath, Ajeet Kumar Yadav, Brinda Bhowmick

{"title":"A novel dual-gate negative capacitance TFET for highly sensitive label free biosensing","authors":"Ravindra Kumar Maurya, Radhe Gobinda Debnath, Ajeet Kumar Yadav, Brinda Bhowmick","doi":"10.1088/1361-6641/ad6eb0","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6eb0","url":null,"abstract":"The negative capacitance (NC) tunnel FET (NCTFET) emerges as a viable choice for the development of highly sensitive biosensors. A dual-gate (DG) structure and n+ doped pocket within the NCTFET is introduced in this study to boost biosensor performance and sensitivity. This research offers a comprehensive and comparative analysis of two biosensor designs: the DG-NCTFET and the n+ pocket-doped DG-NCTFET. Both biosensors feature nanogaps on either side of the fixed dielectric, augmenting their biomolecule capture areas. Sensitivity assessments are conducted considering charged and neutral biomolecules with a range of dielectric constants (<italic toggle=\"yes\">k</italic>). The n+ pocket DG-NCTFET exhibits an <italic toggle=\"yes\">I</italic>ON sensitivity roughly 20 times greater than that of the sensor without a pocket (3.5 × 106 for n+ pocket DG-NCTFET and 1.8 × 105 for DG-NCTFET), primarily because it conducts current in both vertical and lateral directions. Furthermore, for fully filled nanocavity with neutral biomolecules, the maximum <italic toggle=\"yes\">I</italic>ON/<italic toggle=\"yes\">I</italic>OFF sensitivities attained are 1.2 × 105 and 2.8 × 104 for the n+ pocket DG-NCTFET and conventional DG-NCTFET, respectively. Moreover, this research delves into the impact of steric hindrance and the irregular placement of probes, aiming to grasp the non-ideal traits exhibited by the sensors. Significantly, sensitivity experiences a minimal increase of approximately 6<bold>%–</bold>11% when the fill factor escalates from 40% to 66%. In order to set a standard of comparison, the proposed biosensors are benchmarked against existing literature in terms of sensitivity, affirming their efficacy. The findings indicate that the proposed biosensors represent a promising alternative for detecting a wide range of both charged and neutral biomolecules.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"31 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A computational analysis of the impact of thin undoped channels in surface-related current collapse of AlGaN/GaN HEMTs 未掺杂薄沟道对 AlGaN/GaN HEMT 表面相关电流塌陷影响的计算分析

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-08-20 DOI: 10.1088/1361-6641/ad689c

Christos Zervos, Petros Beleniotis, Matthias Rudolph

{"title":"A computational analysis of the impact of thin undoped channels in surface-related current collapse of AlGaN/GaN HEMTs","authors":"Christos Zervos, Petros Beleniotis, Matthias Rudolph","doi":"10.1088/1361-6641/ad689c","DOIUrl":"https://doi.org/10.1088/1361-6641/ad689c","url":null,"abstract":"This study provides an insight into the impact of thin purely undoped GaN channel thickness (<italic toggle=\"yes\">t</italic>ch) on surface-related trapping effects in AlGaN/GaN high electron mobility transistors. Our TCAD study suggests that in cases where parasitic gate leakage is the driving trapping mechanism that promotes the injection of electrons from the Schottky gate contact into surface states, this effect can be alleviated by reducing <italic toggle=\"yes\">t</italic>ch of the undoped GaN channel. We show that by decreasing <italic toggle=\"yes\">t</italic>ch from 130 to 10 nm, devices exhibit a reduction in gate-related current collapse under the specific class-B RF operating bias conditions as a consequence of a substantial decrease in the off-state gate leakage with reducing <italic toggle=\"yes\">t</italic>ch. Large-signal simulations revealed an increase by 3 W mm−1 and about 12% output power and power-added efficiency due to the decrease of gate-related collapse. This work, for the first time, highlights the role of a proper purely undoped GaN <italic toggle=\"yes\">t</italic>ch selection to alleviate gate-related surface trapping in the design of GaN-based microwave power amplifiers.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"11 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study on the regulation factors and mechanism of self-heating effects in non-rectangular 14 nm bulk FinFET* 非矩形 14 纳米块状 FinFET* 中自热效应的调节因素和机理研究

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-08-14 DOI: 10.1088/1361-6641/ad689f

Zhaohui Qin, Lan Chen, Renjie Lu, Yali Wang, Xiaoran Hao, Rong Chen, Yan Sun, Qin Du

引用次数: 0

Influence of power ramps on the physical properties of AZO thin films deposited at room temperature by RF magnetron sputtering technique 功率斜坡对射频磁控溅射技术在室温下沉积的 AZO 薄膜物理性质的影响

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-08-14 DOI: 10.1088/1361-6641/ad6c79

A Cristina Carranza, E Rosendo, H Pérez Ladrón de Guevara, C Morales, R Romano, G García, A Coyopol, R Galeazzi, J Zepeda

引用次数: 0

III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance 基于 III-V 材料的无结型 L 形栅极法线隧道场效应晶体管，可提高性能

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-08-06 DOI: 10.1088/1361-6641/ad689d

Aadil Anam, S Intekhab Amin and Dinesh Prasad

{"title":"III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance","authors":"Aadil Anam, S Intekhab Amin and Dinesh Prasad","doi":"10.1088/1361-6641/ad689d","DOIUrl":"https://doi.org/10.1088/1361-6641/ad689d","url":null,"abstract":"In this paper, we introduce a novel III–V compound material-based junction-free (JF) L-shaped gate normal line tunneling field-effect transistor (III–V JF L GNLTFET) for improved output performance at 0.5 V operation. The key design metric, i.e. JF or junctionless design, in our device eliminates issues like random dopant fluctuations (RDF) and high thermal budgets and streamlines the fabrication. The implementation of III–V compound material, i.e. low bandgap compound GaSb, in the source region, combined with the larger area gate normal line tunneling, improves the ON current for our proposed III–V JF L GNLTFET device. Additionally, the utilization of large bandgap GaAs compounds on the drain and channel sides eliminates ambipolarity and further enhances the performance of our proposed device. Meaning that the proposed device simultaneously improves the ON current and suppresses the ambipolarity. Our proposed III–V JF L GNLTFET exhibits enhanced output performance with an ON current of 23.2 μA μm−1 and a minimum and average subthreshold swing of 3.7 mV dec−1 and 15.82 mV dec−1 respectively. Furthermore, the proposed III–V JF L GNLTFET also gives superior RF/analog performance with transconductance (168.65 μS), cut-off frequency (33.52 GHz), gain-bandwidth product (5.11 GHz), and transconductance-frequency product (243.7 GHz).","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"27 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141946377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improving CZTS/ZTO solar cell efficiency with inorganic BSF layers 利用无机 BSF 层提高 CZTS/ZTO 太阳能电池的效率

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-07-25 DOI: 10.1088/1361-6641/ad6477

Taoufik Chargui, Fatima Lmai, Mohamed Al-Hattab and Khalid Rahmani

{"title":"Improving CZTS/ZTO solar cell efficiency with inorganic BSF layers","authors":"Taoufik Chargui, Fatima Lmai, Mohamed Al-Hattab and Khalid Rahmani","doi":"10.1088/1361-6641/ad6477","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6477","url":null,"abstract":"Copper zinc tin sulfide (CZTS) thin-film solar cells have garnered significant attention in the solar energy sector. This study aims to enhance the performance of CZTS solar cells by replacing the conventional, toxic CdS buffer layer with (ZTO) for x = 0.2. Utilizing the one-dimensional solar cell capacitance simulator (SCAPS-1D) and informed by experimental data on the physical properties of the solar cell layers, we investigated the effects of thickness, doping density, and defect density of the CZTS absorber layer on the cell’s performance. Initially, an efficiency of 14.76% was achieved. To improve this efficiency, an inorganic back surface field (BSF) layer was incorporated to mitigate charge carrier recombination at the absorber/back contact metal interface. Various materials, including CuO, , Mo and Mo , were evaluated as potential BSF layers. Comparative analysis indicated that the inclusion of the BSF layer significantly enhances the solar cell efficiency, achieving up to 27% with as the BSF material. Furthermore, the study included an analysis of temperature effects and parasitic resistances to comprehensively assess the solar cell’s performance.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"15 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures 低温条件下 FDSOI MOSFET 背栅效应的非线性行为

IF 1.9 4区工程技术

Semiconductor Science and Technology Pub Date : 2024-07-11 DOI: 10.1088/1361-6641/ad5e17

Yibo Hu, Zhipeng Ren, Yizhe Yin and Jing Chen

引用次数: 0