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Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92最新文献

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Bare die test 配得上测试
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201438
R. Parker
{"title":"Bare die test","authors":"R. Parker","doi":"10.1109/MCMC.1992.201438","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201438","url":null,"abstract":"The author describes a bare die test approach that uses a temporary interconnect technique overlaid on a reconstructed pseudo-wafer of individual bare dice. This overlay technique maps design-specific pad locations to a standard grid that can be tested with a universal membrane probe. The proposed approach allows the development cost of a thin-film membrane probe to be shared across many die types, thus reducing the cost and complexity of tooling new die types. An experiment performed to validate this approach is described.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122920156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
System partitioning for multi-chip modules under timing and capacity constraints 时序和容量约束下的多芯片模块系统分区
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201464
M. Shih, E. Kuh, R. Tsay
{"title":"System partitioning for multi-chip modules under timing and capacity constraints","authors":"M. Shih, E. Kuh, R. Tsay","doi":"10.1109/MCMC.1992.201464","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201464","url":null,"abstract":"The authors propose an efficient and effective algorithm for system partitioning under timing and capacity constraints. They consider the problem of assigning functional blocks into slots on multi-chip modules in high-level design to have fast feedback on the impact of high-level design decisions. A clustering step is used to ensure timing correctness, followed by packing and the K&L algorithm to satisfy capacity constraints while minimizing net crossings. The method is unique in that net crossings are minimized, while satisfying timing and capacity constraints. Test results showed that the method eliminated timing violations and obtained a comparable number of net crossings to that of the algorithm proposed by C.M. Fiduccia and R.M. Mattheyses (1982) with a similar run time. The method can be extended to use partitioning algorithms other than that of Fiduccia and Mattheyses.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130185642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Effect of humidity cycling on reliability of overlaid high density interconnects 湿度循环对叠加高密度互连可靠性的影响
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201459
X. Shan, R. K. Agarwal, M. Pecht, J. Evans
{"title":"Effect of humidity cycling on reliability of overlaid high density interconnects","authors":"X. Shan, R. K. Agarwal, M. Pecht, J. Evans","doi":"10.1109/MCMC.1992.201459","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201459","url":null,"abstract":"The authors present a finite element simulation, performed to observe the stresses generated in a typical high-density interconnect structure as a result of swelling mismatches due to water absorption. They focus on stresses which could cause de-adhesion and microbuckling of dielectric films due to humidity cycling. Numerical analysis was used to examine the potential failure sites, modes, and failure mechanisms.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116539143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Boundary-scan test structures and test-bench compilation in a multichip module synthesis system 多芯片模块综合系统的边界扫描测试结构及测试台编制
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201443
R. Vutukuru, P. Subbarao, R. Vmuri
{"title":"Boundary-scan test structures and test-bench compilation in a multichip module synthesis system","authors":"R. Vutukuru, P. Subbarao, R. Vmuri","doi":"10.1109/MCMC.1992.201443","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201443","url":null,"abstract":"The authors present a testing methodology for multichip module (MCM) designs, which were automatically generated by a behavioral synthesis system. The testability of the design was enhanced by automatic insertion of boundary scan architecture in every chip of the MCM design. The test vectors for the synthesized design were automatically derived from the behavioral test vectors, which were used to validate the behavioral model of the design. The test vectors were transformed into a serial format as required by the test structures and finally represented in WAVES.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"75 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124636916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Array probe card 阵列探测卡
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201439
M. Beiley, F. Ichishita, C. Nguyen, S. Wong
{"title":"Array probe card","authors":"M. Beiley, F. Ichishita, C. Nguyen, S. Wong","doi":"10.1109/MCMC.1992.201439","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201439","url":null,"abstract":"By utilizing conventional IC processing techniques, a membrane probe card has been fabricated on a silicon wafer and its functionality demonstrated. The probe card was able to provide a very large number of probe tips in an array form, permanently fixed in the X-Y plane via a transparent, flexible membrane. The use of an electrical current pulse, instead of a mechanical scrubbing motion, to break down the interfacial oxide has been demonstrated. The contact resistance was about 5*10/sup -5/ Omega -cm/sup 2/. The new probe card offers smaller probe parasitics. The addition of the active test circuitry on the probe card would allow very high speed wafer level testing.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132605682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Optical interfaces for multichip modules 用于多芯片模块的光接口
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201471
P. Haugsjaa
{"title":"Optical interfaces for multichip modules","authors":"P. Haugsjaa","doi":"10.1109/MCMC.1992.201471","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201471","url":null,"abstract":"An approach to an interconnection scheme for multichip modules (MCMs) based on the use of single-mode optical fiber and long-wavelength (1.3 mu m) semiconductor diode lasers is described. The author considers some of the requirements of a fiber-based interconnection scheme applicable to MCM technology. For MCM interconnection work, many mechanical alignments and materials interfaces can be eliminated by mounting components on a silicon substrate. The development of a silicon waferboard approach has concentrated initially on the development of passively aligned transmitter arrays as a critical test of this technology. The addition of waveguide technology to a silicon waferboard can expand considerably the functionality and flexibility of this technology. Transmitter array development is considered. A completed transmitter array with an array of four passively aligned lasers and fibers along with a GaAs laser driver array is shown.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"461 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134578894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Performance modeling of a cache system with three interconnect technologies: cyanate ester PCB, chip-on-board and Cu/PI MCM 采用三种互连技术的高速缓存系统的性能建模:氰酸酯PCB，片上芯片和Cu/PI MCM
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201467
J. Shiao, D. Nguyen
{"title":"Performance modeling of a cache system with three interconnect technologies: cyanate ester PCB, chip-on-board and Cu/PI MCM","authors":"J. Shiao, D. Nguyen","doi":"10.1109/MCMC.1992.201467","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201467","url":null,"abstract":"To understand the tradeoffs in different interconnect technologies, and to investigate the applicability of MCM (multi-chip module) technology to high performance computer products, an electrical performance modeling study on a cache system using three interconnect technologies was conducted. The three technologies were a high density cyanate ester PCB; chip-on-board; and a copper/polyimide MCM with high-density connectors. Placements and layouts for the cache system, using three interconnect technologies, have been done. Active buffer models and interconnect models have been developed. The performance modeling results, including the interconnect, input/output buffers, critical path delays, and the signal integrity assessment, are presented.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128609234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Multichip module enables for high reliability applications 多芯片模块实现高可靠性应用
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201458
D. Chu, C. Reber, B. Draper, J. Sweet, D. Palmer
{"title":"Multichip module enables for high reliability applications","authors":"D. Chu, C. Reber, B. Draper, J. Sweet, D. Palmer","doi":"10.1109/MCMC.1992.201458","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201458","url":null,"abstract":"To gain uniform, rigorous multichip module (MCM) qualification for high-reliability applications, Sandia has developed: a set of assembly test chips which are available for manufacturers and users to evaluate, characterize, and compare the particular MCM technology in terms of materials, chemical aging, geometries, stress state, thermal management, and assembly techniques; standard interconnect test structures as test coupons on the MCM substrate to determine the aging reliability through accelerated aging and lot quality through statistics; and exhaustive chip pretest methodology through prepackaging in a way compatible with today's military IC packaging assembly lines. The MCM substrate test structures and packaging for chip pretest are discussed.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128432622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Thermal management for ceramic multichip modules: experimental program 陶瓷多芯片模块的热管理:实验程序
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201451
G. Kromann
{"title":"Thermal management for ceramic multichip modules: experimental program","authors":"G. Kromann","doi":"10.1109/MCMC.1992.201451","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201451","url":null,"abstract":"The author describes the thermal characterization of an alumina-tungsten multilayer multichip module (MCM). A five-chip cavity-down MCM was designed to represent a typical substrate product. Thermal test multichip modules were assembled and the thermal performance quantified for both the internal and the external thermal resistances. The die junction-to-ambient resistance was measured in forced-air convection for the range of 1 to 5 m/s, for: (1) two pin-fin heat sinks, (2) a thermoelectric cooler with a pin-fin heat sink, and (3) a heat pipe with an integral extended surface. In addition, the run-to-run and the part-to-part variations, are presented. A discussion on the thermal management concepts and the heat transfer applicable to the MCM technology is included.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123655578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Fully integrated silicon based optical motherboards 完全集成的硅基光学主板
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201470
D. Godfrey, S. Bailey, K. Cooper, M. Nield, J. Hill, D. Welbourn
{"title":"Fully integrated silicon based optical motherboards","authors":"D. Godfrey, S. Bailey, K. Cooper, M. Nield, J. Hill, D. Welbourn","doi":"10.1109/MCMC.1992.201470","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201470","url":null,"abstract":"Optical-fiber-based telecommunications networks require the use of complex optical systems involving semiconductor lasers, detectors, fiber amplifiers, waveguides, and control electronics. A silicon motherboard process technology is described which enables the full range of components to be fabricated on the motherboard (waveguides), mounted on the motherboard (lasers and detectors), or connected to the motherboard (optical fibers or further motherboards). For each element of the overall silicon motherboard process, the fabrication approach used and the optical performance are described. Finally, some potential applications of the technology are outlined.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121084074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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