Boundary-scan test structures and test-bench compilation in a multichip module synthesis system

Abstract

The authors present a testing methodology for multichip module (MCM) designs, which were automatically generated by a behavioral synthesis system. The testability of the design was enhanced by automatic insertion of boundary scan architecture in every chip of the MCM design. The test vectors for the synthesized design were automatically derived from the behavioral test vectors, which were used to validate the behavioral model of the design. The test vectors were transformed into a serial format as required by the test structures and finally represented in WAVES.<>