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Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92最新文献

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Die for MCMs: IC preparation for testing, analysis and assembly mcm模具:用于测试、分析和组装的集成电路准备
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201440
G. Forman, J. Nieznanski, J. Rose
{"title":"Die for MCMs: IC preparation for testing, analysis and assembly","authors":"G. Forman, J. Nieznanski, J. Rose","doi":"10.1109/MCMC.1992.201440","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201440","url":null,"abstract":"A method of die preparation for test, analysis and burn-in is described that can begin to address multichip module (MCM) infrastructure requirements for obtaining known good die. The process developed provides full functional component testing, timing analysis at speed, and burn-in of ICs prior to MCM insertion. A soluble polymer overlay was coated on the die surface and patterned with new top level metal bond pads, allowing standard packaging, testing and burn-in while permitting a method of recovering selected devices for use in an MCM. The overlay formed a protective coating for the die and if left in place may be used to support assembly specific metallization patterns and various metal finish types. A demonstration of this technique is reported and the component quality and analysis effort is described.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116690328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Analysis of MCMs using asymptotic waveform evaluation (AWE) 用渐近波形评估(AWE)分析mcm
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201444
M. M. Alaybeyi, J. Bracken, J.Y. Lee, V. Raghavan, R. Trihy, R. Rohrer
{"title":"Analysis of MCMs using asymptotic waveform evaluation (AWE)","authors":"M. M. Alaybeyi, J. Bracken, J.Y. Lee, V. Raghavan, R. Trihy, R. Rohrer","doi":"10.1109/MCMC.1992.201444","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201444","url":null,"abstract":"Asymptotic waveform evaluation (AWE) is a new method of efficiently analyzing linear circuits. The authors illustrate the applicability of AWE to the analysis of multichip module (MCM) interconnect structures from chip level through packaging, through thick or thin film interconnect and back again. The algorithm is described. Many extensions have been made to the AWE algorithm to render it more suitable for solving large interconnect problems. The use of partitioned solution techniques, a technique for efficiently determining the moments of distributed elements, and the combination of the AWE and SPICE algorithms to handle interconnect problems with general nonlinearities is described. Examples of AWE analysis are included.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125147523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Pade approximation applied to transient simulation of lossy coupled transmission lines Pade近似在损耗耦合传输线暂态仿真中的应用
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201445
S. Lin, E. Kuh
{"title":"Pade approximation applied to transient simulation of lossy coupled transmission lines","authors":"S. Lin, E. Kuh","doi":"10.1109/MCMC.1992.201445","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201445","url":null,"abstract":"A new approach for transient simulation of lossy coupled transmission lines terminated in arbitrary nonlinear elements is presented. The approach is based on convolution simulation. The multiconductor lines are first decoupled to obtain modal functions. Using the Pade approximations of each modal function, the authors derive a recursive convolution formulation, which greatly reduces the computation used to perform convolutions. The approach can handle general coupling situations; no assumption on the simulated circuits is introduced. The approach was implemented in the Stepwise Equivalent Conductance MOS timing simulator, SWEC. The key feature of SWEC is that Newton-Raphson iteration is not needed for the implicit integration of a circuit even with lossy lines terminated in nonlinear elements. The comparisons with SPICE3.e indicated that SWEC can be one to two orders of magnitude faster.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114432770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
MCM prototyping using overlay interconnect process 采用覆盖互连工艺的MCM原型设计
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201441
L. Roszel, W. Daum
{"title":"MCM prototyping using overlay interconnect process","authors":"L. Roszel, W. Daum","doi":"10.1109/MCMC.1992.201441","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201441","url":null,"abstract":"The construction of complex multichip modules requires a means of evaluating the prototype for correct operation and characterization. A flexible prototype method is described, using the overlay interconnect approach, for probing and verification. The overlay process builds the interconnect over the top of a bare die. An overview of the process is given. The overlay interconnect method has several major areas of flexibility that can be used to facilitate the prototyping of MCMs. The ability to access pads, either on the first layer for die verification or on the top layer for control and observation, brings back part of the access for test that was lost in the size reduction. The ability to use the pads to test a partitioned design and then add the final interconnect layer allows current designs to make the transition more easily to the MCM format. Many of the advantages of using the overlay process for prototyping are outlined.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122081875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The reliability performance evaluation of high-density thin-film multichip substrates 高密度薄膜多芯片衬底可靠性性能评价
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201456
J. Yang
{"title":"The reliability performance evaluation of high-density thin-film multichip substrates","authors":"J. Yang","doi":"10.1109/MCMC.1992.201456","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201456","url":null,"abstract":"For the DEC VAX-9000 computer, a high-density interconnect called the high density signal carrier was developed. The author describes the reliability performance evaluation of the high density signal carrier through the phases of the program from the early reliability prediction, through the subsequent reliability assessment and debugging and ongoing reliability testing, to the later analysis of the field reliability performance data. He also reviews and compares the mean time-between-failure (MTBF) design goals versus the actual field performance data over an 18-month period using various reliability assessment methods and techniques.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129110103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A high-speed multi-dielectric capacitance-extraction algorithm for MCM interconnects MCM互连的高速多介质电容提取算法
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201454
Y. Le Coz, R. Iverson
{"title":"A high-speed multi-dielectric capacitance-extraction algorithm for MCM interconnects","authors":"Y. Le Coz, R. Iverson","doi":"10.1109/MCMC.1992.201454","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201454","url":null,"abstract":"The authors report an extension of a stochastic algorithm for capacitance extraction in complex two- and three-dimensional multidielectric structures. The algorithm has applications in the area of circuit modeling of multichip modules. The extension is in the form of a simple probability rule that depends on the ratio of electric permittivities across dielectric interfaces. Computational results are presented for a two-dimensional cross-section of a wire running over a dielectric and ground plane. Results are also presented for a three-dimensional interconnect via partially embedded in a dielectric over a ground plane. All computations were performed on a personal computer. Execution times were nominally five minutes for statistical errors ranging from one to ten percent, depending on dimensionality and value of the dielectric constant. An extraction methodology was devised for large conductor arrays based on superimposing a geometrical hashing grid.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131277416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Bare die testing and MCM probing techniques 裸模测试和MCM探测技术
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201437
D. Keezer
{"title":"Bare die testing and MCM probing techniques","authors":"D. Keezer","doi":"10.1109/MCMC.1992.201437","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201437","url":null,"abstract":"The author discusses two important issues regarding the development and manufacture of multichip modules (MCMs). First, a method is described which is used for testing bare chips at the full operating frequency and over temperature extremes. This approach utilizes a modified wafer probe system and a high-speed digital tester for at-speed performance characterization of individual chips prior to insertion into an MCM. The purpose is to fully assure that the device will perform as required once committed to the module. Second, a system is described for automated internal probing of functioning MCMs. Again, a standard wafer probe system is adapted for this purpose. This system permits characterization of fully populated MCMs.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"66 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122125890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Silicon-on-silicon MCMs with integrated passive components 集成无源元件的硅对硅mcm
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201473
R. Frye, K. Tai, M. Lau, A.W. Lin
{"title":"Silicon-on-silicon MCMs with integrated passive components","authors":"R. Frye, K. Tai, M. Lau, A.W. Lin","doi":"10.1109/MCMC.1992.201473","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201473","url":null,"abstract":"The authors evaluate a prototype silicon-on-silicon multichip module for potential use in cost-driven applications. The incorporation of integrated passive components, resistors and capacitors, in the module substrate is a significant advantage in many of these kinds of applications. A module has been built that incorporates both linear and bipolar and digital CMOS circuits. The unique features of the module are discussed, as well as the properties and performance limits of the resulting passive components.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129199488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Assembly and reliability of micro-scale solder interconnections for flip-chip MCMs 倒装mcm微型焊料互连的组装和可靠性
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201448
T. Dudderar, Y. Degani, N. Nir, A. R. Storm, K. Tai
{"title":"Assembly and reliability of micro-scale solder interconnections for flip-chip MCMs","authors":"T. Dudderar, Y. Degani, N. Nir, A. R. Storm, K. Tai","doi":"10.1109/MCMC.1992.201448","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201448","url":null,"abstract":"The essential features of a high-yield, cost-effective flip-chip multichip module (MCM) fabrication process using automated, whole wafer assembly are discussed. Tests demonstrating (1) superior cleanability of a new AT&T-YD flux as defined by wetting angle measurements and (2) the robust reflow realignment of flip-chip joints assembled using this flux are described and their results reported in detail. Finally, studies of the low-cycle fatigue behavior of flip-chip solder microjoints are presented. The results of this research point the way to designs and processes for the cost effective assembly of reliable flip-chip MCMs.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122217894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Chip on tape qualification and reliability 芯片的质量和可靠性
Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92 Pub Date : 1992-03-18 DOI: 10.1109/MCMC.1992.201450
T. Wang, J. Long, P. Kwong
{"title":"Chip on tape qualification and reliability","authors":"T. Wang, J. Long, P. Kwong","doi":"10.1109/MCMC.1992.201450","DOIUrl":"https://doi.org/10.1109/MCMC.1992.201450","url":null,"abstract":"High-density and high-leadcount chip on tape (COT) technology is emerging as an attractive component for high-performance multichip module applications. A hermetic sealed semiconductor die with gold bump terminations over SiO/sub 2/ and Si/sub 3/N/sub 4/ passivations was bonded to a gold-plated copper tape, using a thermal compression gang bonding technique. The device was subsequently encapsulated and marked. The authors first review the bump design rules, bump characteristics, and the inner lead bond process. The reliability test results of COT devices are presented.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122268394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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