{"title":"芯片的质量和可靠性","authors":"T. Wang, J. Long, P. Kwong","doi":"10.1109/MCMC.1992.201450","DOIUrl":null,"url":null,"abstract":"High-density and high-leadcount chip on tape (COT) technology is emerging as an attractive component for high-performance multichip module applications. A hermetic sealed semiconductor die with gold bump terminations over SiO/sub 2/ and Si/sub 3/N/sub 4/ passivations was bonded to a gold-plated copper tape, using a thermal compression gang bonding technique. The device was subsequently encapsulated and marked. The authors first review the bump design rules, bump characteristics, and the inner lead bond process. The reliability test results of COT devices are presented.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"181 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Chip on tape qualification and reliability\",\"authors\":\"T. Wang, J. Long, P. Kwong\",\"doi\":\"10.1109/MCMC.1992.201450\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High-density and high-leadcount chip on tape (COT) technology is emerging as an attractive component for high-performance multichip module applications. A hermetic sealed semiconductor die with gold bump terminations over SiO/sub 2/ and Si/sub 3/N/sub 4/ passivations was bonded to a gold-plated copper tape, using a thermal compression gang bonding technique. The device was subsequently encapsulated and marked. The authors first review the bump design rules, bump characteristics, and the inner lead bond process. The reliability test results of COT devices are presented.<<ETX>>\",\"PeriodicalId\":202574,\"journal\":{\"name\":\"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92\",\"volume\":\"181 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1992.201450\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1992.201450","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-density and high-leadcount chip on tape (COT) technology is emerging as an attractive component for high-performance multichip module applications. A hermetic sealed semiconductor die with gold bump terminations over SiO/sub 2/ and Si/sub 3/N/sub 4/ passivations was bonded to a gold-plated copper tape, using a thermal compression gang bonding technique. The device was subsequently encapsulated and marked. The authors first review the bump design rules, bump characteristics, and the inner lead bond process. The reliability test results of COT devices are presented.<>
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