{"title":"配得上测试","authors":"R. Parker","doi":"10.1109/MCMC.1992.201438","DOIUrl":null,"url":null,"abstract":"The author describes a bare die test approach that uses a temporary interconnect technique overlaid on a reconstructed pseudo-wafer of individual bare dice. This overlay technique maps design-specific pad locations to a standard grid that can be tested with a universal membrane probe. The proposed approach allows the development cost of a thin-film membrane probe to be shared across many die types, thus reducing the cost and complexity of tooling new die types. An experiment performed to validate this approach is described.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"36","resultStr":"{\"title\":\"Bare die test\",\"authors\":\"R. Parker\",\"doi\":\"10.1109/MCMC.1992.201438\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The author describes a bare die test approach that uses a temporary interconnect technique overlaid on a reconstructed pseudo-wafer of individual bare dice. This overlay technique maps design-specific pad locations to a standard grid that can be tested with a universal membrane probe. The proposed approach allows the development cost of a thin-film membrane probe to be shared across many die types, thus reducing the cost and complexity of tooling new die types. An experiment performed to validate this approach is described.<<ETX>>\",\"PeriodicalId\":202574,\"journal\":{\"name\":\"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"36\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1992.201438\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1992.201438","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The author describes a bare die test approach that uses a temporary interconnect technique overlaid on a reconstructed pseudo-wafer of individual bare dice. This overlay technique maps design-specific pad locations to a standard grid that can be tested with a universal membrane probe. The proposed approach allows the development cost of a thin-film membrane probe to be shared across many die types, thus reducing the cost and complexity of tooling new die types. An experiment performed to validate this approach is described.<>