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2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)最新文献

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Reliability assessment of a large population of 3.3 kV, 45 A 4H-SIC MOSFETs 3.3 kV, 45 a 4H-SIC mosfet的可靠性评估
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988907
E. van Brunt, D. Lichtenwalner, R. Leonard, A. Burk, S. Sabri, B. Hull, S. Allen, J. Palmour
{"title":"Reliability assessment of a large population of 3.3 kV, 45 A 4H-SIC MOSFETs","authors":"E. van Brunt, D. Lichtenwalner, R. Leonard, A. Burk, S. Sabri, B. Hull, S. Allen, J. Palmour","doi":"10.23919/ISPSD.2017.7988907","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988907","url":null,"abstract":"In this work, we report results for the 3 lot, 77 device-per-lot high temperature-reverse bias (HTRB) test, as well as work on gate oxide reliability for 3.3 kV devices in relation to the presence of material defects. The work indicates that large scale reliable operation of 3.3 kV 4H-SIC MOSFETs is achievable using conventional 4H-SiC device processing techniques and DMOS device structures, despite the prevalence of measurable surface morphology on 3.3 kV SiC epilayers. No correlation was found between dislocation content and MOS capacitor breakdown field, measured on over 14 cm2 of combined tested 4H-SIC MOS gate area.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126573043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Highly reliable high-temperature superplastic Al-Zn eutectoid solder joining with stress relaxation characteristics for next generation SiC power semiconductor devices 具有应力松弛特性的高可靠高温超塑Al-Zn共晶焊料连接新一代SiC功率半导体器件
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988887
J. Onuki, A. Chiba, M. Kawakami, Kunihiro Tamahashi, Y. Sugawara, T. Inami, M. Kobiyama, Y. Motohashi, Yuji Kawamata
{"title":"Highly reliable high-temperature superplastic Al-Zn eutectoid solder joining with stress relaxation characteristics for next generation SiC power semiconductor devices","authors":"J. Onuki, A. Chiba, M. Kawakami, Kunihiro Tamahashi, Y. Sugawara, T. Inami, M. Kobiyama, Y. Motohashi, Yuji Kawamata","doi":"10.23919/ISPSD.2017.7988887","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988887","url":null,"abstract":"A new high-temperature lead-free solder joint which withstands temperatures up to 300°C and utilizes superplasticity in an Al-Zn eutectoid alloy has been developed to realize SiC power semiconductor devices. The joining process consists of interfacial cleaning of the joint formed utilizing superplasticity of the Al-Zn-eutectoid alloy at 250°C followed by bonding in the solid-liquid coexisting temperature range in order to control microstructures and to reduce occurrence of voids. The developed SiC/SiN substrate joints with void-free and stress relaxation effects show outstanding reliability in temperature cycle tests from −40°C to 300°C for 5000 cycles.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124237116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Investigation of current collapse mechanism of LPCVD Si3N4 passivated AlGaN/GaN HEMTs by fast soft-switched current-DLTS and CC-DLTFS 用快速软开关电流dts和CC-DLTFS研究LPCVD Si3N4钝化AlGaN/GaN hemt的电流坍塌机制
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988919
Xinhua Wang, X. Kang, Jinhan Zhang, K. Wei, Sen Huang, Xinyu Liu
{"title":"Investigation of current collapse mechanism of LPCVD Si3N4 passivated AlGaN/GaN HEMTs by fast soft-switched current-DLTS and CC-DLTFS","authors":"Xinhua Wang, X. Kang, Jinhan Zhang, K. Wei, Sen Huang, Xinyu Liu","doi":"10.23919/ISPSD.2017.7988919","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988919","url":null,"abstract":"In this work, we investigated the current collapse mechanism of AlGaN/GaN high-electron mobility transistors (HEMTs) with LPCVD Si3N4 passivation. With newly developed fast soft-switched current-DLTS techniques, we achieved current acquisition within 100 ns after each stress pulse and with high sampling rate up to 5 MSa/s. A single trap level (∼66 meV) and capture cross section On (−1.05×10−20 cm−2) has been found within the AlGaN/GaN HEMTs surface. Moreover, this trap level is confirmed by low-temperature Constant-Capacitance Deep-Level Transient Fourier Spectroscopy (CC-DLTFS) measurement on GaN MIS-diode structure. Although this trap level is quite shallow, it can still lead to current collapse in LPCVD-SiNx-passivated AlGaN/GaN HEMTs due to the small On.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131804607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new sub-micron trench cell concept in ultrathin wafer technology for next generation 1200 V IGBTs 超薄晶圆技术中的亚微米沟槽电池概念，用于下一代1200v igbt
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988895
C. Jaeger, A. Philippou, Antonio Ve Ilei, J. Laven, Andreas Härtl
{"title":"A new sub-micron trench cell concept in ultrathin wafer technology for next generation 1200 V IGBTs","authors":"C. Jaeger, A. Philippou, Antonio Ve Ilei, J. Laven, Andreas Härtl","doi":"10.23919/ISPSD.2017.7988895","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988895","url":null,"abstract":"The overall growing trend towards electrification and, at the same time, the urgent need to minimize energy consumption strongly requires higher energy efficiency in power electronics. We present a new technology concept for next generation 1200 V IGBTs with vastly reduced overall power losses using an optimized micro-pattern trench (MPT) cell design with sub-micron mesas. Further important parameters relevant for inverters driving electrical machines were optimized, including turn-off softness, dv/dt-controllability, and short circuit capability, providing a right-fit solution to customer requirements.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130470877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Characterization of X-ray radiation hardness of diamond Schottky barrier diode and metal-semiconductor field-effect transistor 金刚石肖特基势垒二极管和金属半导体场效应晶体管的x射线辐射硬度表征
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988983
H. Umezawa, S. Ohmagari, Y. Mokuno, J. Kaneko
{"title":"Characterization of X-ray radiation hardness of diamond Schottky barrier diode and metal-semiconductor field-effect transistor","authors":"H. Umezawa, S. Ohmagari, Y. Mokuno, J. Kaneko","doi":"10.23919/ISPSD.2017.7988983","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988983","url":null,"abstract":"Diamond has attracted extensive attention for the next generation semiconductor devices, such as high-power, low-loss and high-frequency devices under high temperature conditions. In this paper, a radiation hardness of diamond unipolar devices such as Schottky barrier diode (SBD) and metal-semiconductor field-effect transistor (MESFET) was discussed. No any degradation of ideality factor or specific on-resistance of diamond SBD was observed even after 10 MGy X-ray irradiation. The breakdown voltage was increased after the irradiation since the leakage current increased. The forward current capability and the transconductance of MESFET were almost constant to the X-ray irradiation.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122288601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Application opportunities and expectations for wide bandgap power devices in power supply 宽禁带功率器件在电源中的应用机遇与展望
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988980
Z. Zhao, Chaofeng Cai, Tao Wang
{"title":"Application opportunities and expectations for wide bandgap power devices in power supply","authors":"Z. Zhao, Chaofeng Cai, Tao Wang","doi":"10.23919/ISPSD.2017.7988980","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988980","url":null,"abstract":"In this paper, the evolvement of power supply with wide bandgap semiconductor, including SiC and GaN devices, is reviewed. Different circuit features are analyzed with unique device characteristics. By employing GaN HEMTs, the power convertor hardware is compared with conventional design. The detailed architecture of convertor is given to evaluate the trend of the next generation power convertors enabled by wide bandgap devices. Practical design is implemented to prove high elïîciency and high density with simplified circuit and auto-manufactory. Based on the analysis of hardware, some relevant issues are discussed in the following part, regarding the technical challenges for the application of SiC/GaN and further optimization targeting different applications.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"365 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132740024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new 1200 V-class edge termination structure with trench double field plates for high dV/dt performance 新型1200v级边缘端接结构，采用沟槽双场板，具有高dV/dt性能
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988938
Wentao Yang, Hao Feng, Yong Liu, Xiangming Fang, Y. Onozawa, Hiroyuki Tanaka, Kaname Mitsuzuka, J. Sin
{"title":"A new 1200 V-class edge termination structure with trench double field plates for high dV/dt performance","authors":"Wentao Yang, Hao Feng, Yong Liu, Xiangming Fang, Y. Onozawa, Hiroyuki Tanaka, Kaname Mitsuzuka, J. Sin","doi":"10.23919/ISPSD.2017.7988938","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988938","url":null,"abstract":"In this paper, a new 1200 V-class edge termination structure with trench double field plates is proposed and experimentally demonstrated. The double field plates are buried inside the trench. One of the field plates is for modulating electric field distributions along the trench and shifting the breakdown point to the active region for achieving the ideal planar junction breakdown voltage, and the other one is for stopping the depletion region extension at the right side of the trench to achieve high dV/dt performance. The fabricated device has a breakdown voltage of 1422 V which is verified as the ideal planar junction breakdown voltage. Furthermore, it is with a record-short edge termination length of 78 μm which is less than one-fifth of conventional guard ring approaches. Besides, it can handle a high dV/dt value of 73 kV/μs even at a bus voltage of 1400 V.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114072144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Riddle and Bond Silicon on Insulator (RABSOI) 绝缘体上的谜和键硅(RABSOI)
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988950
R. Spetik, Filip Kudrna, L. Valek
{"title":"Riddle and Bond Silicon on Insulator (RABSOI)","authors":"R. Spetik, Filip Kudrna, L. Valek","doi":"10.23919/ISPSD.2017.7988950","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988950","url":null,"abstract":"In this paper, a novel method for creation of Partial Silicon on Insulator (PSOI) substrate is divulged. The PSOI substrate may be thereafter utilized as a starting material for power integrated technologies where both dielectrically isolated devices as well as backside electrically and / or thermally connected devices are required on the same die. Disclosed method relies predominantly on standard manufacturing process steps utilized for regular SOI production such as wafer bonding, grinding and polishing.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114364668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Best-in-class LDMOS with ultra-shallow trench isolation and p-buried layer from 18V to 40V in 0.18μm BCD technology 采用0.18μm BCD技术，具有超浅沟槽隔离和18V至40V p埋层的同类最佳LDMOS
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988962
Feng Jin, Donghua Liu, Junjun Xing, Xinjie Yang, Jiye Yang, W. Qian, Wei Yue, Pengfei Wang, M. Qiao, Bo Zhang
{"title":"Best-in-class LDMOS with ultra-shallow trench isolation and p-buried layer from 18V to 40V in 0.18μm BCD technology","authors":"Feng Jin, Donghua Liu, Junjun Xing, Xinjie Yang, Jiye Yang, W. Qian, Wei Yue, Pengfei Wang, M. Qiao, Bo Zhang","doi":"10.23919/ISPSD.2017.7988962","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988962","url":null,"abstract":"This paper proposes a novel LDMOS structure with ultra-shallow trench isolation (USTI) and p-buried layer in 0.18um BCD technology platform. This platform offers 18V to 40V LDMOS devices which has best-in-class specific on-resistant (R<inf>on, sp</inf>) with respect to similar technologies. USTI structure is implemented in LDMOS drift region to reduce specific on-resistance (R<inf>on, sp</inf>) by shortening the current flow path and smooth the surface electric field. Meanwhile P-buried layer is introduced to assist depletion and enhance the charge density of drift region, which reduces R<inf>on, sp</inf> further and keep higher breakdown. The R<inf>on, sp</inf> of proposed USTI-LDMOS devices is very competitive, 18V LDMOS has BV<inf>DSS</inf>=27V and R<inf>on, sp</inf>=7.1 mΩ·mm<sup>2</sup>; 20V LDMOS has BV<inf>DSS</inf>=30V and R<inf>on, sp</inf>=8.8mΩ·mm<sup>2</sup>; 30V LDMOS has BV<inf>DSS</inf>=42V and R<inf>on, sp</inf>=14.5mΩ·mm<sup>2</sup>; 40V LDMOS has BV<inf>DSS</inf>=52V and R<inf>on, sp</inf>=20.5mΩ·mm<sup>2</sup>.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116047235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Novel superjunction LDMOS with multi-floating buried layers 新型多浮埋层超结LDMOS
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988959
Zhen Cao, B. Duan, Song Yuan, Haijun Guo, Jianmei Lv, Tongtong Shi, Yintang Yang
{"title":"Novel superjunction LDMOS with multi-floating buried layers","authors":"Zhen Cao, B. Duan, Song Yuan, Haijun Guo, Jianmei Lv, Tongtong Shi, Yintang Yang","doi":"10.23919/ISPSD.2017.7988959","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988959","url":null,"abstract":"In this paper, a novel superjunction lateral double-diffused MOSFET (SJ-LDMOS) based on the bulk electric field modulation is proposed. The new structure is characterized by adding the multiple floating buried layers (MFBL) into the substrate/epitaxial layer. In this way, the high bulk electric field under the drain diffusion edge is reduced and the overall bulk electric field distribution is optimized. In addition, the N+/P-substrate junction and the auxiliary MFBL/substrate junctions jointly sustain a high breakdown voltage (BV). Simulated results show that the BV of MFBL SJ-LDMOS is improved by about 80.4% than that of the buffered step doping (BSD) SJ-LDMOS with the same drift region length. Furthermore, compared with the N-type buffered SJ-LDMOS the BV of MFBL SJ-LDMOS significantly increases by 131.7%. Moreover, the power figure-of-merit (FOM=BV2/RON, sp) of MFBL SJ-LDMOS reaches 13.07 MW/cm2 with the excellent performance breaking the silicon limit.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114595913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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