Best-in-class LDMOS with ultra-shallow trench isolation and p-buried layer from 18V to 40V in 0.18μm BCD technology

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI:10.23919/ISPSD.2017.7988962

Feng Jin, Donghua Liu, Junjun Xing, Xinjie Yang, Jiye Yang, W. Qian, Wei Yue, Pengfei Wang, M. Qiao, Bo Zhang

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引用次数: 21

Abstract

This paper proposes a novel LDMOS structure with ultra-shallow trench isolation (USTI) and p-buried layer in 0.18um BCD technology platform. This platform offers 18V to 40V LDMOS devices which has best-in-class specific on-resistant (Ron, sp) with respect to similar technologies. USTI structure is implemented in LDMOS drift region to reduce specific on-resistance (Ron, sp) by shortening the current flow path and smooth the surface electric field. Meanwhile P-buried layer is introduced to assist depletion and enhance the charge density of drift region, which reduces Ron, sp further and keep higher breakdown. The Ron, sp of proposed USTI-LDMOS devices is very competitive, 18V LDMOS has BVDSS=27V and Ron, sp=7.1 mΩ·mm²; 20V LDMOS has BVDSS=30V and Ron, sp=8.8mΩ·mm²; 30V LDMOS has BVDSS=42V and Ron, sp=14.5mΩ·mm²; 40V LDMOS has BVDSS=52V and Ron, sp=20.5mΩ·mm².

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采用0.18μm BCD技术，具有超浅沟槽隔离和18V至40V p埋层的同类最佳LDMOS

在0.18um BCD技术平台上，提出了一种具有超浅沟隔离(USTI)和p埋层的新型LDMOS结构。该平台提供18V至40V的LDMOS器件，具有同类技术中最佳的特定导通电阻(Ron, sp)。在LDMOS漂移区采用USTI结构，通过缩短电流通路和平滑表面电场来降低比导通电阻(Ron, sp)。同时引入埋p层辅助损耗，提高漂移区电荷密度，进一步降低Ron、sp，保持较高的击穿。提出的USTI-LDMOS器件的Ron, sp具有很强的竞争力，18V LDMOS的BVDSS=27V, Ron, sp=7.1 mΩ·mm2;20V LDMOS的BVDSS=30V, Ron, sp=8.8mΩ·mm2;30V LDMOS的BVDSS=42V, Ron, sp=14.5mΩ·mm2;40V LDMOS的BVDSS=52V, Ron, sp=20.5mΩ·mm2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)

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