Best-in-class LDMOS with ultra-shallow trench isolation and p-buried layer from 18V to 40V in 0.18μm BCD technology

This paper proposes a novel LDMOS structure with ultra-shallow trench isolation (USTI) and p-buried layer in 0.18um BCD technology platform. This platform offers 18V to 40V LDMOS devices which has best-in-class specific on-resistant (Ron, sp) with respect to similar technologies. USTI structure is implemented in LDMOS drift region to reduce specific on-resistance (Ron, sp) by shortening the current flow path and smooth the surface electric field. Meanwhile P-buried layer is introduced to assist depletion and enhance the charge density of drift region, which reduces Ron, sp further and keep higher breakdown. The Ron, sp of proposed USTI-LDMOS devices is very competitive, 18V LDMOS has BVDSS=27V and Ron, sp=7.1 mΩ·mm²; 20V LDMOS has BVDSS=30V and Ron, sp=8.8mΩ·mm²; 30V LDMOS has BVDSS=42V and Ron, sp=14.5mΩ·mm²; 40V LDMOS has BVDSS=52V and Ron, sp=20.5mΩ·mm².