{"title":"绝缘体上的谜和键硅(RABSOI)","authors":"R. Spetik, Filip Kudrna, L. Valek","doi":"10.23919/ISPSD.2017.7988950","DOIUrl":null,"url":null,"abstract":"In this paper, a novel method for creation of Partial Silicon on Insulator (PSOI) substrate is divulged. The PSOI substrate may be thereafter utilized as a starting material for power integrated technologies where both dielectrically isolated devices as well as backside electrically and / or thermally connected devices are required on the same die. Disclosed method relies predominantly on standard manufacturing process steps utilized for regular SOI production such as wafer bonding, grinding and polishing.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Riddle and Bond Silicon on Insulator (RABSOI)\",\"authors\":\"R. Spetik, Filip Kudrna, L. Valek\",\"doi\":\"10.23919/ISPSD.2017.7988950\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a novel method for creation of Partial Silicon on Insulator (PSOI) substrate is divulged. The PSOI substrate may be thereafter utilized as a starting material for power integrated technologies where both dielectrically isolated devices as well as backside electrically and / or thermally connected devices are required on the same die. Disclosed method relies predominantly on standard manufacturing process steps utilized for regular SOI production such as wafer bonding, grinding and polishing.\",\"PeriodicalId\":202561,\"journal\":{\"name\":\"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/ISPSD.2017.7988950\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/ISPSD.2017.7988950","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, a novel method for creation of Partial Silicon on Insulator (PSOI) substrate is divulged. The PSOI substrate may be thereafter utilized as a starting material for power integrated technologies where both dielectrically isolated devices as well as backside electrically and / or thermally connected devices are required on the same die. Disclosed method relies predominantly on standard manufacturing process steps utilized for regular SOI production such as wafer bonding, grinding and polishing.