Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.最新文献

{"title":"New anisotropic conductive film (ACF)","authors":"A. Yokoyama, K. Maehara, K. Takagi","doi":"10.1109/EPTC.2003.1298744","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298744","url":null,"abstract":"Asahikasei has originally developed the new conductive powder AMG/sup R/ which has a specific structure mainly composed of copper and a small amount of silver, wherein its particle's surface is quite rich in silver component in spite of containing a small amount of silver throughout the particle. The configuration of AMG are summarized here: (1) the Cu-Ag alloy powder is mainly composed of copper and a small amount of silver; (2) the particle surface is rich in silver component; (3) the shape is nearly spherical. Thanks to this specific structure, AMG shows excellent performance, such as high electroconductivity due to its composition of copper and silver, excellent reliability and less ion-migration because of its specific structure when applied to ACF.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134058737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Value added technology development on microinterconnect flex circuit","authors":"Z. Ke","doi":"10.1109/EPTC.2003.1298730","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298730","url":null,"abstract":"To develop a conductive polymer formulation which can be printed through an automatic reel-to-reel process to form a thin film (0.1 to 25 /spl mu/m) on insulated materials. The materials can be but not limited to, polymers, engineering plastic, ceramics, glasses, fibers, hard coating layers, especially on microinterconnect flex circuits (1 to 10 mil in total thickness with or without organic cover coating materials) made from polyimide or LCP (Liquid crystal polymers) substrates. A thin conductive film will significantly reduce surface resistivity of the coated surfaces to a range of 10E5 to 10 E9 ohms. The thickness of the film can be adjusted through a cliche design (Pad printing) with a dimensional alignment control at +/- 10-20%, or through mesh design by using screen-printing technique when there is a need in covering small features (200 /spl mu/m). The printing process is a reel-to-reel high volume-manufacturing line. To develop an Reel-To-Reel automatic solder ball (100 to 700,/spl mu/m)jetting process for the thin film microinterconnect flex circuits (1 to 10 mil) in supporting advance flex circuit application for Chip on Flex (COF), Chip On Suspension (COS), Piezo elements (PZT) Attachment, especially on FSA/HGA manufacturing (Flex Suspension Assembly, and Head Gimbal Assembly).","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127097286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Developments and trends in stacked die CSPs","authors":"E. J. Vardaman","doi":"10.1109/EPTC.2003.1298711","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298711","url":null,"abstract":"With increased demand for small form factor packages for portable products there has been increased demand for dense packaging. Stacking dice inside the CSP is one solution. This presentation focuses on CSPs with multiple dies stacked inside.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115673323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation and optimization of solution flow in fountain-plating cup for Au bumping","authors":"T. Hu, Shuidi Wang, Haining Wang, Jian Cai, Songliang Jia","doi":"10.1109/EPTC.2003.1298703","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298703","url":null,"abstract":"A fountain-plating cup is designed and fabricated in IMETU (Institute of Microelectronics, Tsinghua University). The simulation and optimization of solution flow in the cup by computational fluid dynamics (CFD) tool have been introduced in this paper. The structure of the plating cup is presented and the position, the thickness and the hole size of the diffuser and the velocity of flow at entrance are used as the parameters for simulation. With the results of the simulation, Au bumps with tolerance in /spl plusmn/2.5 /spl mu/m on a 6 inch wafer have been fabricated.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117123674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of ultrasonic flip chip bonding on flex substrates","authors":"H. Schafer, P. Yuan, Z. Wang","doi":"10.1109/EPTC.2003.1298715","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298715","url":null,"abstract":"Most commonly used flip chip on foil technique for display applications is based on Anisotropic Conductive Film (ACF). In this technique, ACF is laminated onto the substrate before an IC is aligned and placed under high temperature. The ACF is then cured under pressure. Conductive particles trapped between the bumps of the IC and Cu tracks on the substrate forms electrical connections; while the adhesive ensures mechanical integrity. With the pitch becomes smaller and smaller, ACF technique is no longer capable to provide reliable connections due to the limitation in particle size and density and thus high risks in. open and short. Ultrasonic flip chip is developed as one of the potential techniques for ultra-fine pitch COF applications. In this technique, ultrasonic energy is applied through the bonding head to the bump/track interfaces. The relative moment results in localized high temperature which promotes the welding of two surfaces, to form mechanical and electrical connections. In this paper, the experimental results on ultrasonic flip chip on foil will be reported Au bumped test ICs were used The bumps were in rectangular shape with the length of typically 80/spl mu/m. The smallest pitch of the test ICs was 40/spl mu/m. Two layer adhesiveless polyimide based flex circuit substrates were de signed and used as the test vehicles for the investigation. Ni/Au were plated on the Cu tracks. The bonding process was optimized to achieve reliable interconnections. The critical parameters in ultrasonic bonding include ultrasonic energy, pressure, stage temperature, time and sequence of underfilling. High assembly yield was achieved with the optimized parameter settings. Thermal shock test and high accelerated stress test were conducted. It was shown that reliable interconnections can be formed using the ultrasonic bonding technique for fine pitch applications. However, considering the machine accuracy, bumps co-planarity, and displacement amplitude in the bonding process, further investigation is required for applications of less than 30/spl mu/m pitch.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116127944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solder ball joints: voiding, qualification and mechanical issues","authors":"T. Collier","doi":"10.1109/EPTC.2003.1298774","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298774","url":null,"abstract":"Solder ball failure can be caused by a number of technicalities. The three common root causes that lead to package failure are inadequate qualification, mechanical issues (typically due to IMC formation) and solder voiding (due to poor processes). To deliver acceptable customer performance, the process designer needs to understand the interactions of variables that can result in time zero as well as latent failure.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121257976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cracking prediction of IC's passivation layer using J-integral","authors":"Y.T. He, G.Q. Zhang, W.D. van Drie, X.J. Fan, L. Ernst","doi":"10.1109/EPTC.2003.1298761","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298761","url":null,"abstract":"Passivation layer cracks in ICs are often observed. The interfaces between compound or metal lines and passivation layers form typical corners, with two materials involved. The J-integral around the corner tip is presented as the passivation layer cracking criterion here, which is called modified J-integral criterion. With this modified J-integral criterion and the fracture toughness of passivation material, the passivation layer cracking can be predicted. Finite Element Method(FEM) is employed in this paper to calculate the J-integral by means of energy release rate. And the passivation corner J-integral value and most possible cracking direction are predicted for a given example.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123882492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability and new failure modes of encapsulated flip chip on board under thermal shock testing","authors":"C. Bo, Wang Li, Zhang Qun, Gao Xia, Xie Xiaoming, W. Kempe","doi":"10.1109/EPTC.2003.1298772","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298772","url":null,"abstract":"The thermomechanical reliability of flip chip on board (FCOB) assembly under thermal shock test is addressed in this paper by investigation of different material/process combinations (underfill, flux, reflow atmospheres). It is verified that solder fatigue is the dominate failure mechanism and delamination has obvious adverse effect on the solder joint lifetime. Periodic solder joint crack is first reported in this study and is determined to be related to glass fiber distribution in the PCB.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116565858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The brazing of metal-ceramic insulator package","authors":"Wangchen Tu, Chuanzhen Chen, Kai Wangluning","doi":"10.1109/EPTC.2003.1298726","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298726","url":null,"abstract":"With the development of the IC technology, the metal-ceramic insulator package is widely used in IC packaging and gradually develop a series of products, which play an important role in package field. Despite the type of the package differ from each other, the basic structure is same. A metal-ceramic insulator is usually consist of a base, a frame, leads, solder and ceramic insulator which is produced by means of brazing. In following passage, it takes JF04F3 package as an example to make detailed introduction.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132349709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Metallurgy and stability of the Sn/Cu interface for lead-free flip chip application","authors":"R. Shih, D. Lau, R. Kwok","doi":"10.1109/EPTC.2003.1298743","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298743","url":null,"abstract":"Eutectic tin copper and pure tin are two possible candidates to replace tin lead alloy as the solder bump materials for the flip-chip process. Without lead, the stability of the Sn/Cu interface during reflow suffers from the rapid dissolution of copper into molten tin. The requirements of multiple reflow during the flip-chip manufacturing steps further complicate the issue. This study aims to better understand the metallurgy and stability of the bump/copper substrate interface and compares the results to a Sn/Ni interface. A tin-copper bump with 0.7-1 wt% of copper and pure tin bumps were electroplated using a fountain plating machine on silicon wafers with copper and nickel as the under bump metal. The samples were pre-annealed at various temperatures and multiple reflows were performed using a 5-zones reflow-oven. The cross-sections of the interfaces were studied by scanning electron microscopy and scanning Auger microscopy. It was found that copper dissolution into the eutectic tin copper and pure tin solders during the reflow process resulted in the formation of Cu/sub 6/Sn/sub 5/ intermetallic at the interface. The ball shear test result suggests that the presence of the intermetallic at the interface did not adversely affect the bonding strength of the bump/copper interface. In this study, we developed a pre-annealing process to control the intermetallic region that can significantly slow down the copper dissolution during reflow.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125485163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}