Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.最新文献

{"title":"Non-hermetic opto-electronic packaging based on micro-machined silicon bench platform","authors":"Sheng Liu, Z. Gan, Xiansong. Chen, Jia Zhaol, Hou Bin","doi":"10.1109/EPTC.2003.1298719","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298719","url":null,"abstract":"Non-hermetic opto-electronic packaging, coupled with passive coupling, provides the direction for reducing the cost of automating packaging and assembly processes, without sacrificing the overall reliability. In this paper, we discuss the process of establishing the platform for the first time in China, which includes the material selection and evaluation, process development that includes silicon bench micro-machining and solder pad metallization, solder film deposition, laser diode bonding, UV-curing, matching fluid dispensing, glob-top encapsulation, and silicon bench bonding on the board. Numerical and experimental tools are used for the optical, thermal, and mechanical performance of the packaging design and manufacturing. In particular, Monte Carlo simulation was used to predict that 100% can be achieved when the flip-chip post-bonding accuracy can be maintained to be within 2 /spl mu/m in in the plane direction and 1 /spl mu/m in the out-of-plane displacement control. Results for an innovative MiniDIL TOSA/ROSA and a transceiver module are discussed.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125401516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Water absorption and corrosion protection of esterified novolac resin cured epoxy resins applicable for microelectronics packing","authors":"Shanjun Li, Xiaolin Tang, Yifu Ding, M. Liu","doi":"10.1109/EPTC.2003.1298756","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298756","url":null,"abstract":"In the present work, to study the effects of side group on water absorption, a series of novolac epoxy resins was cured with esterified a phenol novolac resin and phenol novolac resins separately. Thus, the hydroxyl group of phenol novolac resin was replaced by CH/sub 3/COO- group, C/sub 3/H/sub 7/COO/spl rho/oup and C/sub 6/H/sub 5/CH/sub 2/COO- group, and the cured resins were named as EP, EPA, EPB and EPP, respectively. FTIR showed that there were no hydroxyl groups but ester functional groups in the cured resins cured. with the esterified phenol novolac resins. The influence of the side groups on the water absorption behavior of the cured epoxy resins was investigated using gravimetric method, DSC, and corrosion test.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134603518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A systematic evaluation of thermal performance of interface materials in high power amplifiers","authors":"L. Maguire, M. Behnia, G. Morrison","doi":"10.1109/EPTC.2003.1298780","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298780","url":null,"abstract":"A comprehensive study has been undertaken to better understand the thermal conditions within high power, radio frequency (r.f.) signal amplifiers. Here, the results of investigation of the interface thermal resistance between the primary heat dissipating transistors and the heat sink are presented. With individual devices dissipating up to 130W each, junction temperatures have been shown to approach 200/spl deg/C when ambient temperatures reach 60/spl deg/C. Under these conditions the interface thermal resistance currently accounts for 20% of the total drop from junction to ambient temperature. Experiments were conducted to determine the interface thermal resistance of a number of candidate materials allowing comparison of application specific data obtained here with the manufacturer published data. The data was also used to compare the performance of the current thermal grease compound with several commercially available alternatives. At maximum power dissipation, transistor temperatures were reduced by up to 20/spl deg/C through the use of a high conductivity thermal grease in conjunction with careful preparation of the contact surfaces to ensure consistent flatness.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124005242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New proposed adhesive tape application mechanism for stacking die applications","authors":"Y. Cheung, A. Chong","doi":"10.1109/EPTC.2003.1298748","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298748","url":null,"abstract":"One approach to develop a high-density electronic package for memory modules is stacking the dice in the packaging and assembly processes. The development of the stacked die has been speeded up significantly in recent years by the maturity of the wafer thinning technology. Conventionally, if the top die and bottom dice are the same size, a dummy silicon die is used as a spacer to separate the dice and make room for wire bonding. Methods including using a much thicker epoxy or epoxy with spacer balls would be the alternative techniques. A new technique has been developed recently. A thick adhesive tape of size a bit smaller than the die is used as spacer as well as adhesive for the bonding of the bottom and top dice. This new process, known as adhesive tape application process, is introduced for stacking the dice. In the process, a predetermined tape size is cut, picked and placed on the top surface of the bottom die or substrate. The advantages of this technique over the dispensing process are (i) there is no die tilt and (ii) there are no epoxy bleed out issues. However, there may be new issues, such as delamination failure that occurs at the bonding interface. In this study, we find that void formation due to trapped air in the bonding interface is introduced by the tape application process while a collet with flat surface is used to place the tape on the bottom die or substrate. The uneven contact points between tape and bonding surface trap air bubbles in the bonding interface. We invent a new tape application tool that can basically eliminate trapped air bubbles during the tape bonding process. A convex compliant collet is used to pickup and place the tape on the bonding surface: The line contact between tape and bonding surface is formed in the middle of the tape. The air is not trapped in the bonding interface as the collet moves further down to deform the collet and squeeze the tape out sideways. Finite element simulation has been carried out to determine the optimized configuration in terms of force requirements to flatten the convex collet, strain/stress distribution of the compliant collet and the tape itself. Selection criteria of this compliant material for the tape application process are also discussed. Experiments have been carried out to verify the void-free condition is achieved using this new convex compliant collet.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124272218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stress-strain simulation of solder joints in a BGA package","authors":"Cheng Yan, Y. Mai, L. Ye","doi":"10.1109/EPTC.2003.1298694","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298694","url":null,"abstract":"A nonlinear finite element analysis was carried out to investigate the viscoplastic deformation of solder joints in a ball grid array (BGA) package under temperature cycling. The effects of constraint on print circuit board (PCB) and stiffness of substrate on the deformation behaviour of the solder joints were also studied The results indicated that high inelastic strain was developed in the joints close to the package center. On the other hand, high constraint was associated with the joint closest to the edge of the silicon chip. Increasing external constraint on the PCB caused a slight increase in stress triaxiality in the joint closest to the edge of silicon chip. There was an increase of inelastic strain in the solder joints with increasing the Young's modulus of the substrate.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116729136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The delamination of solder ball involving moisture and thermal effect in IC package","authors":"Jun Wang, F. Xiao","doi":"10.1109/EPTC.2003.1298699","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298699","url":null,"abstract":"The difference of CTE leads to stress concentration at the interface in the package. The underfill material is wildly used for reducing the mismatch of CTE in the flip chip package. Moreover, the ingress of moisture in underfill material will affect the failure behaviour of solder ball. In this paper, the analysis of solder ball delamination involving thermal and moisture concentration is performed. The results demonstrate that the moisture concentration can not be ignored in reflow, especially in lower temperature range. The swelling coefficient of moisture is additional factor assist delamination except mismatch of CTE during solder reflow.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116885616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenges and advances in use-condition-based mechanical reliability test development","authors":"L. Mercado, S. Sahasrabudhe, E. Monroe","doi":"10.1109/EPTC.2003.1298762","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298762","url":null,"abstract":"With rapid advances in the electronic packaging technology, reliability tests based on field conditions have become essential to the package reliability assessment. This paper discusses some major challenges and recent advances in both the assembly and end use condition characterizations and reliability test development.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128969473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Research on failure modes of BGA assemblies with lead-free solder on different PCB materials","authors":"Fangjuan Qi, Jim Liu","doi":"10.1109/EPTC.2003.1298769","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298769","url":null,"abstract":"Emerging environmental regulations worldwide, most notably in Europe and Japan, have targeted the elimination of Pb usage in electronic assemblies, due to the inherent toxicity of Pb. Similarly the toxicity of halogen based PCBs in landfills has also prompted the industry as well as various governments to work toward the introduction of halogen-free PCBs in electronics. So research on the reliability and failure mode of BGA assembly with lead-free on different PCB materials including traditional FR4 material and new environmental halogen-free materials are very important in order to speed up their application in electronic. In this paper, firstly the mechanical bend fatigue reliability was studied by the Mini-Mechanical Tester (MMT) system. Then the failure mode was studied by cross sectional method. The results show that two failure modes were found for lead-free and halogen-free assembly. One is crack through, halogen free material and the other is crack in lead-free solder. For lead-free and FR4 assembly, two failure modes were also found. One is crack in solder and the other is crack in the copper trace. Considering the mechanical bend fatigue reliability of these two assemblies, when crack initiate from solder materials, the reliability of assembly with lead-free solder on halogen-free shows higher than that of assembly with lead-free solder on FR4. For the assembly with lead-free on halogen-free, the obvious law was found that the halogen-free material failure was the main failure in short life and the lead-free solder failure is the main failure mode in long life area. However there is no obvious law for the assembly with lead-free on FR4.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127728003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New fluorinated polyimides for advanced microelectronic applications","authors":"Jingang Liu, M. He, Z. Ge, L. Fan, Shi-yong Yang","doi":"10.1109/EPTC.2003.1298747","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298747","url":null,"abstract":"A series of fluorinated polyimide films have been prepared by casting the poly (amic acid) solution, which were synthesized by polycondensation of 4,4-(hexafluoroisopropylidene) diphthalic anhydride (6FDA) with various fluorinated aromatic diamines, including 1,4-bis (4-amino-2-trifluoromethylphenoxy) benzene (p6FPB), 4-[3', 5'-bis-(trifluoromethyl) phenyl]-2,6-bis (4\"-amino-phenyl) pyridine (pTFPP) and 4-[3',5'-bis-(trifluoromethyl phenyl)-2,6-bis (3\"-aminophenyl) pyridine] (mTFPP), followed by thermal imidization at elevated temperatures. The strong and flexible polyimide films, PI-1 (6FDA-p6FPB), PI-2 (6FDA-pTFPP) and PI-3 (6FDA-mTFPP) exhibited good thermal stability and high mechanical properties. The films also showed high surface and volume resistances and low dielectric constant. The excellent combined properties of the materials make them great candidates for microelectronic packaging.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128441703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Surface finishes in PWB fabrication","authors":"K. Song, J. Liu","doi":"10.1109/EPTC.2003.1298788","DOIUrl":"https://doi.org/10.1109/EPTC.2003.1298788","url":null,"abstract":"With the density of surface mount components increasing, ball grid array packaging (BGA) has become used more widely. The increased requirements on surface finish of printed wiring boards (PWB) turns out to be an even more important factor in current fabrication processes. In this paper, we introduced state of the art predominant finishes technologies and discussed their pros and cons. In addition, we show some related failure cases, which provide strong support for the above claim.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131395340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}