T. Hu, Shuidi Wang, Haining Wang, Jian Cai, Songliang Jia
{"title":"Simulation and optimization of solution flow in fountain-plating cup for Au bumping","authors":"T. Hu, Shuidi Wang, Haining Wang, Jian Cai, Songliang Jia","doi":"10.1109/EPTC.2003.1298703","DOIUrl":null,"url":null,"abstract":"A fountain-plating cup is designed and fabricated in IMETU (Institute of Microelectronics, Tsinghua University). The simulation and optimization of solution flow in the cup by computational fluid dynamics (CFD) tool have been introduced in this paper. The structure of the plating cup is presented and the position, the thickness and the hole size of the diffuser and the velocity of flow at entrance are used as the parameters for simulation. With the results of the simulation, Au bumps with tolerance in /spl plusmn/2.5 /spl mu/m on a 6 inch wafer have been fabricated.","PeriodicalId":201404,"journal":{"name":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC.2003.1298703","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A fountain-plating cup is designed and fabricated in IMETU (Institute of Microelectronics, Tsinghua University). The simulation and optimization of solution flow in the cup by computational fluid dynamics (CFD) tool have been introduced in this paper. The structure of the plating cup is presented and the position, the thickness and the hole size of the diffuser and the velocity of flow at entrance are used as the parameters for simulation. With the results of the simulation, Au bumps with tolerance in /spl plusmn/2.5 /spl mu/m on a 6 inch wafer have been fabricated.