{"title":"A candid comparison of the SWEAT technique and the conventional test procedure for electromigration study in sub-half micron ULSI interconnects","authors":"S. S. Menon, R. Choudhury","doi":"10.1109/IRWS.1997.660291","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660291","url":null,"abstract":"The thicknesses of the various layers forming the TiN-AlCu-TiN stack were varied and the impact on reliability was studied using the SWEAT technique (Root and Turner, Int. Reliability Physics Symp., 1985) along with the conventional electromigration procedure for 0.35 /spl mu/m SWEAT structures and interconnects respectively. The SWEAT results indicated that the lifetime correlates well with the AlCu thickness, while the TiN thicknesses were relatively unimportant. The conventional test procedure indicated that the lifetime correlates well with the bottom TiN thickness or even the sum of the bottom and top TiN thicknesses, while the AlCu thickness was relatively less important. It is understood that when the AlCu layer opens up during the electromigration test, the TiN acts as a shunt to prolong conductor life and that a thicker TiN layer does this better, provided that the current density is not extremely high. The relatively high current density associated with the SWEAT procedure does not allow for this mechanism, and the lifetime is almost entirely dependent on the AlCu properties. Therefore, the conventional test procedure is good for reliability estimation, while process monitoring (especially AlCu properties) may be done using the SWEAT procedure.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114239508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transformation of charge-to-breakdown obtained from ramped current stresses into charge-to-breakdown and time-to-breakdown domains for constant current stress","authors":"N. A. Dumin","doi":"10.1109/IRWS.1997.660307","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660307","url":null,"abstract":"Summary form only given. Charge-to-breakdown (Q/sub BD/) is one of the parameters that is used as a measure of gate oxide quality. It has been shown that, under the correct measurement conditions, there is good agreement between the Q/sub BD/ that is measured with an exponential current ramp (ECR) and the Q/sub BD/ that is measured with a constant current stress (CCS), and that Q/sub BD/ depends strongly on the ramp rate of the exponential current ramp and the current density of the constant current stress (Dumin, Int. Integrated Reliability Workshop Final Report, 1997). Previous work has shown that the breakdown distribution obtained from a linear voltage ramp can be transformed into the constant voltage stress TDDB domain for time-to-breakdown (Berman, Int. Reliability Physics Symp., pp. 204-209, 1981). Similar to this, a method is presented here for transformation of the Q/sub BD/ distribution obtained from exponential ramp experiments into the constant current stress TDDB domains of time-to-breakdown (t/sub BD/) and Q/sub BD/.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132753825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Q/sub bd/ dependence on stress and test structure parameters: A review","authors":"A. Martin, P. O'Sullivan, A. Mathewson","doi":"10.1109/IRWS.1997.660310","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660310","url":null,"abstract":"This paper gives a review of charge-to-breakdown data which has been reported in the literature for SiO/sub 2/ layers grown on single crystalline silicon. The different trends of charge-to-breakdown characteristics monitored for various stress conditions and structure designs are discussed. This work demonstrates that a good understanding of the stress method, the stress parameters and the test structures is essential for the correct interpretation of the charge-to-breakdown.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116006871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Discussion Group Summary Wafer Level Reliability (WLR)","authors":"C. Messick, S. Yankee","doi":"10.1109/IRWS.1997.660299","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660299","url":null,"abstract":"ATTENDANCE could be used to effectively measure reliability of a fa.b’s products. Representatives of the FSA were present to respond to questions and to clarify objectives of the project. After the discussion, the consensus of the groups was that The WLR discussion group was well-attended, averaging approximately 25 persons per night. As expected, some lively discussion ensued from these groups, which represented many different facets of the semiconductor industry.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124696299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability test chips: NIST 33 and NIST 34 for JEDEC inter-laboratory experiments and more","authors":"H. Schafft","doi":"10.1109/IRWS.1997.660312","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660312","url":null,"abstract":"Two reliability test patterns, NIST 33 and NIST 34, are being designed, and a third, NIST 36, is being planned to be used in a number of inter-laboratory experiments as part of the activities of the Metal Reliability Task Group of the EIA/JEDEC Committee JC 14.2 on Wafer Level Reliability. These chips will also be used for other tasks, many of which will provide additional characterization data in support of the JEDEC inter-laboratory experiments.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128293438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automated analysis of MOS-C relaxation time for WLR testing","authors":"D. Monroe, S. Swanson","doi":"10.1109/IRWS.1997.660303","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660303","url":null,"abstract":"Summary form only given. The relaxation time of a metal oxide semiconductor capacitor (MOS-C) is the time required for the restoration of thermal equilibrium, after being pulsed into deep depletion. Relaxation time has become widely used for monitoring wafer processing, because it is sensitive to the presence of contaminants. This paper describes and compares two automated techniques for analysis of capacitor relaxation-time data to determine the mean generation lifetime, /spl tau//sub g/, for electron-hole pairs. The first technique is an enhanced version of an existing method, while the second is a new technique that requires much less data processing and is much more reliable as an automated analysis tool.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130089318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Correlation of charge-to-breakdown obtained from constant current stresses and ramped current stresses, and the implications for ultra-thin gate oxides","authors":"N. A. Dumin","doi":"10.1109/IRWS.1997.660288","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660288","url":null,"abstract":"Charge-to-breakdown (Q/sub BD/) is one of the parameters that is used as a measure of oxide quality. In this work, the influence of the measurement conditions on Q/sub BD/ is examined, as well as the relationship between Q/sub BD/ and oxide thickness. Using oxides ranging from 45 /spl Aring/ to 80 /spl Aring/, two Q/sub BD/ measurement methods are employed: constant current stress and exponential current ramp. A variety of current densities (for the constant current stress) and delay times (for the exponential current ramp) are studied. It is shown that not only does Q/sub BD/ depend on oxide thickness, but that Q/sub BD/ depends strongly on the measurement conditions, and that depending on the test conditions, Q/sub BD/ can increase or decrease as the oxide thickness decreases. It is also shown that there is a strong agreement between the Q/sub BD/ measured with a constant current stress and the Q(BD) measured with an exponential current ramp. Finally, the equipment-related limitations of the exponential current ramp are discussed, as well as the impact these limitations have on the underestimation of the resulting Q/sub BD/.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131680627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Plasma-induced polarity dependent hot-carrier response of CMOS devices across a wafer","authors":"V. Janapaty, B. Bhava, S. Kerns, N. Bui","doi":"10.1109/IRWS.1997.660273","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660273","url":null,"abstract":"In this study, plasma-processed devices are subjected to hot-carrier stressing experiments to evaluate the reliability across the wafer. Devices with N/sup +/-P, P/sup +/-N, both N/sup +/-P and P/sup +/-N diodes, and no protection diode, are used to establish the nature of the injection (gate and substrate) conditions across the wafer. Results show that P-channel devices subjected to gate injection during plasma processing show higher degradation than those subjected to substrate injection. N-MOSFETs subjected to gate injection during plasma processing show a higher antenna ratio dependence than those subjected to substrate injection. Also, a linear relationship is observed between the pre-stress trapped positive charge in the oxide and threshold voltage shift after hot-carrier stress. Gate injection during plasma processes creates higher trapped positive charge and hence the hot-carrier lifetime of devices subjected to gate injection can be significantly lower than that of devices subjected to substrate injection.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117257029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Discussion Group Summary Reliability Test Structures","authors":"T. Turner","doi":"10.1109/IRWS.1997.660301","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660301","url":null,"abstract":"The Reliability Test Structure Discussion Group covered a range of topics. The first issue was the use of test structures. In general it was agreed that test structures were used both for production monitoring and for qualification testing. The test structures used for production monitoring were generally smaller and fit into scribe lanes or a few drop in die. Larger areas were generally available for structures intended for qualification testing. New process qualification, process change qualification and new equipment qualification testing can often be tested using special “qualification wafers” with large areas covered with test structures. These use test structure die that occupy large parts of a reticule, generally areas in multiples of a die area. These structures can be used to address “defect density” issues which contribute to infant mortality problems as well as wearout failure mechanisms.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123503845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new algorithm for circuit-level electrothermal simulation under EOS/ESD stress","authors":"T. Li, C. Tsai, Y. Huh, E. Rosenbaum, S. Kang","doi":"10.1109/IRWS.1997.660305","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660305","url":null,"abstract":"Summary form only given. ESD protection circuits are designed to meet certain specifications such as human body model (HBM) voltage. Electrothermal circuit simulation can be of use in protection circuit design. In this work, we propose a new algorithm to evaluate transient device temperatures, such as the drain junction temperature of NMOS devices, so that the electrothermal circuit simulation can be performed accurately. Using the electrothermal circuit simulator, we can examine device heating during HBM testing.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130585549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}