可靠性测试芯片:NIST 33和NIST 34用于JEDEC实验室间实验等

1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI:10.1109/IRWS.1997.660312

H. Schafft

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引用次数: 2

摘要

两种可靠性测试模式，NIST 33和NIST 34，正在设计中，第三种，NIST 36，正在计划用于一些实验室间实验，作为EIA/JEDEC委员会JC 14.2关于晶圆级可靠性的金属可靠性任务组活动的一部分。这些芯片还将用于其他任务，其中许多将提供额外的表征数据，以支持JEDEC实验室间实验。

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Reliability test chips: NIST 33 and NIST 34 for JEDEC inter-laboratory experiments and more

Two reliability test patterns, NIST 33 and NIST 34, are being designed, and a third, NIST 36, is being planned to be used in a number of inter-laboratory experiments as part of the activities of the Metal Reliability Task Group of the EIA/JEDEC Committee JC 14.2 on Wafer Level Reliability. These chips will also be used for other tasks, many of which will provide additional characterization data in support of the JEDEC inter-laboratory experiments.

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1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)

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