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1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)最新文献

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Discussion Group Summary Customer Reliability Requirements 讨论小组总结客户可靠性要求
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660300
I. Wylie, A. Preussger
{"title":"Discussion Group Summary Customer Reliability Requirements","authors":"I. Wylie, A. Preussger","doi":"10.1109/IRWS.1997.660300","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660300","url":null,"abstract":"According to most (1 1) of the participants the delivered reliability is on average improving. Only 5 thought that this is not the case. Again like the expectations this point of view may differ with respect to market segments or between large and small suppliers. Even in those cases where the reliability is stable with respect to a delivered IC it had increased because of the increasing complexity of todays ICs. Another aspect is that because of better reliability models and physical understanding on the supplier side the reliability safety margin although being smaller is better known. There was no clear statement whether the technical understanding of reliability issues is becoming more confused (6) stays constant (2) or is improved (7) on the customer side. So customer education and partnership at reliability items is still an important target especially for the small companies. The larger companies improved their knowledge a lot by taking on technical reliability experts. Nevertheless there is still a hstration with fickle customer standards as a customer argued about his colleagues.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"17 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125716752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Degradation of the characteristics of p/sup +/ poly MOS capacitors with NO nitrided gate oxide due to post nitrogen annealing 后氮退火对NO氮化栅氧化物p/sup +/聚MOS电容器性能的影响
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660311
M. K. Mazumder, A. Teramoto, K. Kobayashi, M. Sekine, S. Kawazu, H. Koyama
{"title":"Degradation of the characteristics of p/sup +/ poly MOS capacitors with NO nitrided gate oxide due to post nitrogen annealing","authors":"M. K. Mazumder, A. Teramoto, K. Kobayashi, M. Sekine, S. Kawazu, H. Koyama","doi":"10.1109/IRWS.1997.660311","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660311","url":null,"abstract":"Summary form only given. Wet oxides annealed in NO ambient for two different temperatures and degradation due to post N/sub 2/ annealing on the characteristics of p/sup +/ poly MOS capacitors have been investigated. Results show that samples with N/sub 2/ post annealing at 900/spl deg/C have a large increase in leakage current and charge trapping compared with samples without N/sub 2/ post annealing. Although NO annealing improves the SiO/sub 2/-Si interface, post annealing in N/sub 2/ at a high temperature of 900/spl deg/C for 30 minutes may diffuse boron from the p/sup +/ poly to the gate oxide, and hence degrades the characteristics of p/sup +/ poly Si gate oxide.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127583098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A practical statistical technique to improve seal integrity and reliability of microelectronic packages 提高微电子封装密封完整性和可靠性的实用统计技术
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660302
T.R. Narasimhan, E. Trotter
{"title":"A practical statistical technique to improve seal integrity and reliability of microelectronic packages","authors":"T.R. Narasimhan, E. Trotter","doi":"10.1109/IRWS.1997.660302","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660302","url":null,"abstract":"This paper presents insights into the variability of the functionality, quality and reliability characteristics of hermetically sealed packages for electronic applications. Process characterization and analysis methods are shown on packages from a true production environment. The concept of statistical models and filtering is given to depict the output variables (leak rate, residual gas analysis) and to define process leak limits derived from characterization instead of arbitrary limits set by military standards. Process monitoring (SPC) via statistical charts (standard deviation and median) maintains the on-going control. The leak limit set by process control totally eliminates fluid ingress in packages and moisture related corrosion failures compared to fixed military standard limits. This statistical technique is easy to implement and has potential usefulness in new applications such as assessing new methods and configurations of hermetically sealed enclosures. By preventing moisture induced corrosion, long term reliability is improved significantly.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133790254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Evolution of BSIM3v3 parameters during hot-carrier stress 热载流子应力下BSIM3v3参数的演化
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660297
S. Minehane, P. O'Sullivan, A. Mathewson, B. Mason
{"title":"Evolution of BSIM3v3 parameters during hot-carrier stress","authors":"S. Minehane, P. O'Sullivan, A. Mathewson, B. Mason","doi":"10.1109/IRWS.1997.660297","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660297","url":null,"abstract":"One of the key components in any circuit reliability simulation methodology is a strategy for predicting the hot-carrier-induced changes in device parameters during stress. A novel direct parameter extraction strategy for the BSIM3v3 MOSFET model, and its application to hot-carrier reliability simulation, is presented in this paper. The use of direct techniques produces physically-relevant SPICE parameters from a minimum number of device I-V measurements. The change in the parameter values during hot-carrier stress exhibit a more monotonic trend than those obtained using conventional parameter optimization techniques. The application of a direct SPICE parameter extraction scheme to the hot-carrier reliability problem also makes the extraction routines repeatable over a wide range of experimental conditions. A new approach for the fitting of the evolution of directly-extracted BSIM3v3 parameters during stress is presented.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133532870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Automated extraction of parasitic BJTs for CMOS I/O circuits under ESD stress 静电放电下CMOS I/O电路寄生bjt的自动提取
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660296
T. Li, Y. Huh, S. Kang
{"title":"Automated extraction of parasitic BJTs for CMOS I/O circuits under ESD stress","authors":"T. Li, Y. Huh, S. Kang","doi":"10.1109/IRWS.1997.660296","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660296","url":null,"abstract":"The layout of chip I/O heavily relies on design expertise and guidelines due to the lack of supporting CAD tools. Visual inspection of layout by experts to pinpoint design or layout flaws is common industrial practice for I/O verification. In order to meet industrial demand for I/O verification tools, we have developed a layout extractor which targets the reliability issues of CMOS chip I/Os, with specific emphasis on electrostatic discharge (ESD). In this paper, we present an automated systematic approach for identification of parasitic bipolar junction transistors (BJTs) under ESD stress. The extracted circuit netlist can be simulated by an ESD circuit-level simulator.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125764179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
CMOS transistor reliability and performance impacted by gate microstructure 栅极微结构对CMOS晶体管可靠性和性能的影响
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660278
B. Yu, T. King, C. Hu, D. Ju, N. Kepler
{"title":"CMOS transistor reliability and performance impacted by gate microstructure","authors":"B. Yu, T. King, C. Hu, D. Ju, N. Kepler","doi":"10.1109/IRWS.1997.660278","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660278","url":null,"abstract":"This paper investigate the impact of CMOS (complementary metal-oxide-semiconductor) gate microstructure on the reliability and performance of deep-submicrometer CMOS transistors. The amorphous silicon (/spl alpha/-Si) gate provides better capability for suppression of boron penetration in p/sup +/ doped gate p-channel MOSFETs, but gate depletion in the /spl alpha/-Si gate is slightly more severe than that of the poly-Si gate. The gate-length-dependent gate-depletion effect, in which the difference in linear g/sub m/ between MOSFETs with two different gate microstructures shows a strong L/sub g/-dependence, is reported and interpreted by impurity diffusion along the grain boundary. A gate nitrogen implant as an effective method for suppression of the boron diffusion is also discussed with emphasis on the impact on both device reliability and performance.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131442331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Designing-in device reliability during the development of high-performance CMOS logic technology to 0.13 /spl mu/m 设计期间开发的高性能CMOS逻辑技术将器件可靠性提高到0.13 /spl mu/m
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660279
D. Nayak, M. Hao, R. Hijab
{"title":"Designing-in device reliability during the development of high-performance CMOS logic technology to 0.13 /spl mu/m","authors":"D. Nayak, M. Hao, R. Hijab","doi":"10.1109/IRWS.1997.660279","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660279","url":null,"abstract":"During the development of advanced CMOS process technology, the trade-off between high performance and reliability is being made in each generation of technology. In this work, we present these trade-offs as the CMOS devices are scaled from 0.5 /spl mu/m-generation to 0.13 /spl mu/m-generation technology.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134514783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study on the Al/silicon rich oxide/Si structure as a surge suppresser 富铝/富硅氧化物/硅结构浪涌抑制剂的研究
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660306
M. Aceves, J. Pedraza, J. Apolinar Reynoso-Hernandez, C. Falcony, W. Calleja
{"title":"Study on the Al/silicon rich oxide/Si structure as a surge suppresser","authors":"M. Aceves, J. Pedraza, J. Apolinar Reynoso-Hernandez, C. Falcony, W. Calleja","doi":"10.1109/IRWS.1997.660306","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660306","url":null,"abstract":"Summary form only given. The off-stoichiometry silicon oxide, or silicon rich oxide (SRO), also known as semi-insulating polysilicon (SIPOS), is a material formed by SiO/sub 2/ with excess Si (Dong et al, J. Electrochem. Soc. vol. 125, no. 5, p. 819, 1978). This material is normally obtained by CVD with silane and nitrous oxide as the reactive gases. In modern IC technology, input (or output) ESD protection is a major limitation to further increases in circuit integration. The two main effects are the large area consumption, and the high frequency limitation imposed by the input cell size needed for this application. One possible solution to this problem is that the input pad by itself behaves as an input protection. To achieve this function, the input pad must be able to provide a conduction path to the substrate for low frequency voltages above a given value, and also must be able to handle the very high frequency characteristics of the ESD transients. The I-V characteristics of Al-SRO-Si suggest the possibility of using this device as a surge suppresser, and it may be possible to substitute an input pad for a device that does not use more area than a simple pad. This paper presents a study of the I-V relationship of the Al-SRO-Si structure from low to medium frequencies and under the human body model spike generator. It is shown that this device may be used as a low frequency surge suppresser and that more work must be done to determine whether it can be used as an input protection for ICs.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"43 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134120874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Temperature dependence of gate current in ultra thin SiO/sub 2/ in direct-tunneling regime 超薄SiO/sub - 2/直接隧道状态下栅极电流的温度依赖性
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660282
A. Yassine, R. Hijab
{"title":"Temperature dependence of gate current in ultra thin SiO/sub 2/ in direct-tunneling regime","authors":"A. Yassine, R. Hijab","doi":"10.1109/IRWS.1997.660282","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660282","url":null,"abstract":"In this paper, we examine the temperature dependence of gate current in the direct tunneling regime in ultra thin oxide MOS capacitors under positive and negative gate bias. It was found that for temperature above /spl sim/348 K and low fields, the gate current is exponentially dependent on 1/T. In this temperature range, it was found that gate current is dominated by a thermionic-type of emission current. However, below /spl sim/348 K, the gate current is weakly dependent on temperature and is dominated by field activated direct tunneling. This finding holds for PMOS and NMOS devices operating in accumulation and inversion. The activation energies for the thermionic-type emission for different gate voltage conditions were determined from the Arrhenius plots to be between 0.64 eV and 0.84 eV for PMOS and between 0.73 eV and 0.82 eV for NMOS. It was also found that the activation energy decreases with increasing gate voltage. In addition, it was found that the activation energy is lower for injection from p-type electrodes than that for injection from n-type electrodes.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132306573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Charge-to-breakdown and trap generation process in thin oxides 薄氧化物中的电荷击穿和陷阱生成过程
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660284
G. Bersuker, J. Werking, D. Chan
{"title":"Charge-to-breakdown and trap generation process in thin oxides","authors":"G. Bersuker, J. Werking, D. Chan","doi":"10.1109/IRWS.1997.660284","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660284","url":null,"abstract":"In the proposed model, trap generation is assumed to be triggered by the collision of injected electrons with oxide atoms. The model suggests that thinner oxides are less susceptible to charging stress due to both lower probability of electron collision and lower electron impact energy. The difference in positive and negative gate bias charge-to-breakdown data is attributed to the formation of a structural transition layer at the Si-SiO/sub 2/ interface. The model is used for analysis of the effects of process induced charging damage on transistor parameters. It is found that after heavy stress, leakage current is determined by the probability of trap assisted tunneling, while the density of generated traps controls leakage in lightly damaged oxides.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"376 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132912918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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