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1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)最新文献

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High resolution electromigration measurements for reduction of the test time 高分辨率电迁移测量，减少测试时间
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660292
C. De Keukeleire, L. Tielemans, P. De Pauw
{"title":"High resolution electromigration measurements for reduction of the test time","authors":"C. De Keukeleire, L. Tielemans, P. De Pauw","doi":"10.1109/IRWS.1997.660292","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660292","url":null,"abstract":"This paper presents a faster method to assess the electromigration performance of metal tracks. The method is based on high accuracy measurements (in the PPM range) which allow monitoring of resistance variations in NIST metal tracks. It is shown that, due to the high accuracy, differences in degradation can be observed after a relatively short stress time and the failure criterion for time-to-failure (TTF) can be decreased. By decreasing the failure criterion for resistance changes from the typical range of 20 to 30% to a range of 1 to 5%, electromigration test time can be reduced by a factor of four. It was also shown that reducing the failure criterion has no impact on the determined values of thermal activation energy E, and current acceleration factor n. Finally, a new strategy is proposed: by using a 1% failure criterion for determination of E/sub a/ and n (at 3 temperatures and 3 current densities) and a 30% failure criterion for determination of the cumulative failure curve (1 temperature and 1 current density), the total test time duration can be reduced by a factor of four and provides the same information than a conventional electromigration test.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"378 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125139878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Resistance transients in thin-film noise data [IC interconnects] 薄膜噪声数据中的电阻瞬变[IC互连]
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660272
L. Head
{"title":"Resistance transients in thin-film noise data [IC interconnects]","authors":"L. Head","doi":"10.1109/IRWS.1997.660272","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660272","url":null,"abstract":"Noise measurements taken under accelerated stressing conditions do not work for the prediction of VLSI interconnect lifetime. This is because a crucial feature of the resistance changes under accelerated bias, which could provide insight into metallization reliability, is obscured by spectral analysis. Distinctive resistance transients occur sporadically during accelerated life testing and it is the presence of these transients that make Fourier analysis inappropriate. Recent work has shown that abrupt changes of resistance (ACRs) in a DC biased thin metal film can be correlated with voiding processes. It is the sensitivity of a measurement system designed to detect very low level noise fluctuations that allows one to detect these small resistance changes. The analysis of this data from a time-domain perspective has great potential for advancing the understanding of damage processes in metallization. This presentation provides details of the detection of resistance transients, evidence of their correlation to voiding processes, and data from a detection system designed to monitor the transients.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128042321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Antenna damage from a plasma TEOS deposition reactor: Relationship with surface charge and RF sensor measurements 等离子体TEOS沉积反应器的天线损伤:与表面电荷和射频传感器测量的关系
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660276
I. Gupta, K. Taylor, D. Buck, S. Krishnan
{"title":"Antenna damage from a plasma TEOS deposition reactor: Relationship with surface charge and RF sensor measurements","authors":"I. Gupta, K. Taylor, D. Buck, S. Krishnan","doi":"10.1109/IRWS.1997.660276","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660276","url":null,"abstract":"We identified antenna damage associated with a PECVD (plasma enhanced chemical vapor deposition) TEOS (tetraethoxysilane) process for interlevel dielectric deposition. The damage was isolated to the terminating steps in the recipe depositing 1000 /spl Aring/ of SiO/sub 2/. V/sub s/ (surface charge) measurements on the Keithley Quantox along with our CMOS test chip were used for further characterization of the terminating steps. At the same time, an RF sensor was used to identify the plasma characteristics of the chamber. A design of experiments was done around the RF power and chuck-to-wafer spacing in the terminating sequence in order to minimize damage to the antenna.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130642013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Determination of physical parameters and reliability of ultra thin oxides 超薄氧化物物理参数和可靠性的测定
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660314
E. Cartier
{"title":"Determination of physical parameters and reliability of ultra thin oxides","authors":"E. Cartier","doi":"10.1109/IRWS.1997.660314","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660314","url":null,"abstract":"Summary form only given. The aggressive downscaling of CMOS device dimensions requires the fabrication of gate oxides in the 2-3 nm range in the near future. The accuracy and sensitivity of numerous experimental techniques may soon lead to difficulties in measuring physical parameters such as the oxide thickness or the densities of stress induced defects required to quantify oxide degradation and to understand dielectric breakdown. In this presentation, commonly used methods for measurement of oxide thickness were critically reviewed and some recent efforts to obtain higher accuracy for thickness measurements were discussed. Similarly, the limitations of the more conventional methods for defect generation measurement were discussed and one powerful alternative which can only be used in thin oxides was introduced. It was shown how this method, stress induced leakage current measurement, can be related to the oxide degradation and can be used to understand oxide breakdown. The dominant role played by hydrogen in the degradation process was illustrated.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125273172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Discussion Group Summary Report Designing in Reliability - Dir 讨论小组总结报告可靠性设计-主任
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660298
M. Poulter, W. Vigrass
{"title":"Discussion Group Summary Report Designing in Reliability - Dir","authors":"M. Poulter, W. Vigrass","doi":"10.1109/IRWS.1997.660298","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660298","url":null,"abstract":"Process Qualification without Product Qualification. The traditional method of qualifying a new process comes late in the development cycle. It is achieved by running qualification on a few lots of a product that exercises the main features of the process. If there are failures, much time and money is wasted in implementing process improvements and performing requalification. In the constant push to reduce development cycle times, methods must be implemented to start qualification of the process well in advance of any product. Identifying and fixing reliability problems early avoids the need for costly requalification and the unacceptable delays it incurs.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114898815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel in-process wafer-level screening technique for CMOS devices 一种新的CMOS晶圆级制程筛选技术
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660293
I. Yoshii, K. Hama, H. Hazama, H. Kamijo, Y. Ozawa
{"title":"A novel in-process wafer-level screening technique for CMOS devices","authors":"I. Yoshii, K. Hama, H. Hazama, H. Kamijo, Y. Ozawa","doi":"10.1109/IRWS.1997.660293","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660293","url":null,"abstract":"We have developed a novel in-process wafer-level screening technique to eliminate CMOS device infant mortality due to gate oxide defects. Using this technique, it is possible to stress all gate oxides simultaneously at an arbitrary high voltage for both n-channel and p-channel transistors. This paper describes the details of the screening method and its application to the standard 0.8 /spl mu/m CMOS logic technology. The result shows that early TDDB failures are significantly reduced by this technique.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131213987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Benchmarking semiconductor manufacturing 对标半导体制造
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660271
R. Leachman, D. Hodges
{"title":"Benchmarking semiconductor manufacturing","authors":"R. Leachman, D. Hodges","doi":"10.1109/IRWS.1997.660271","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660271","url":null,"abstract":"We are studying the manufacturing performance of semiconductor wafer fabrication plants in the US, Asia, and Europe. There are great similarities in production equipment, manufacturing processes, and products produced at semiconductor fabs around the world. However, detailed comparisons over multi-year intervals show that important quantitative indicators of productivity, including defect density (yield), major equipment production rates, wafer throughput time, and effective new process introduction to manufacturing, vary by factors of 3 to as much as 5 across an international sample of 28 fabs. We conduct on-site observations, and interviews with manufacturing personnel at all levels from operator to general manager, to better understand reasons for the observed wide variations in performance. We have identified important factors in the areas of information systems, organizational practices, process and technology improvements, and production control that correlate strongly with high productivity. Optimum manufacturing strategy is different for commodity products, high-value proprietary products, and foundry business.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115353002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Pulsed bias temperature stress-An accurate and fast technique to determine mobile ion concentrations in gate and field oxides 脉冲偏置温度应力-一种精确、快速测定栅极和场氧化物中移动离子浓度的技术
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660294
L. Gutai
{"title":"Pulsed bias temperature stress-An accurate and fast technique to determine mobile ion concentrations in gate and field oxides","authors":"L. Gutai","doi":"10.1109/IRWS.1997.660294","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660294","url":null,"abstract":"Mobile ion contamination is a recurring reliability problem in MOS integrated circuit technology. In this paper, we suggest a fast and simple technique to determine the ion concentrations and kinetics by measuring the threshold voltage shift of an active or field MOS transistor after high temperature bias stress at the stress temperature. The I/sub D/ vs. V/sub GS/ characteristics are measured with a pulsed sweep voltage applied to the gate. Between the pulses, the gate voltage is switched back to the stress bias value in order to restore the prepulse ion concentrations at the interfaces. By avoiding the time consuming and cumbersome heating/cooling cycles of the traditional BTS technique and making use of the exponential time dependency of the threshold voltage shift, the test can be executed in less than 60 seconds.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125070111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimized application of antenna structures in a WLR monitoring program [IC testing] 天线结构在WLR监测项目中的优化应用[IC测试]
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660277
J. Fazekas, W. Asam, J. von Hagen
{"title":"Optimized application of antenna structures in a WLR monitoring program [IC testing]","authors":"J. Fazekas, W. Asam, J. von Hagen","doi":"10.1109/IRWS.1997.660277","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660277","url":null,"abstract":"When using antenna structures in a wafer-level reliability production monitoring program, we must take into account some restrictive conditions with regard to the available space for the required test structures and the time allowed for testing them. The purpose of this investigations was to find arguments for efficient selection of test structures and an appropriate choice of evaluation tests.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125497254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Device design methodology and reliability strategy for deep sub-micron technology [DRAMs] 深亚微米技术[dram]器件设计方法与可靠性策略
1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI: 10.1109/IRWS.1997.660315
R. Divakaruni, B. El-Kareh, W. Tonti
{"title":"Device design methodology and reliability strategy for deep sub-micron technology [DRAMs]","authors":"R. Divakaruni, B. El-Kareh, W. Tonti","doi":"10.1109/IRWS.1997.660315","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660315","url":null,"abstract":"This tutorial paper discusses device and process optimization techniques that may be employed in the design of current state-of-the-art bulk silicon DRAM technology. MOSFET performance and reliability issues are contrasted.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122374610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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