1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)最新文献

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Investigation of the intrinsic SiO/sub 2/ area dependence using TDDB testing 利用TDDB测试研究SiO/sub / area的内在依赖关系
J. Prendergast, N. Finucane, J. Suehle
{"title":"Investigation of the intrinsic SiO/sub 2/ area dependence using TDDB testing","authors":"J. Prendergast, N. Finucane, J. Suehle","doi":"10.1109/IRWS.1997.660275","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660275","url":null,"abstract":"To date, there has been very little comprehensive work done on the area dependence of MOS capacitors using time dependent dielectric breakdown testing. The area dependence was investigated by Sune et al. (Thin Solid Films vol. 185, pp. 347-362, 1990) and it indicated that it existed for Q/sub bd/ and potentially for TDDB. Recent work at IRPS'97 tutorials also indicated the same TDDB dependence but these investigations were limited by either the range of areas investigated or the range of test conditions used. This paper provides a thorough investigation into oxide area dependence over 5 orders of magnitude using multiple temperatures and electric fields in order to understand the breakdown mechanism, failure statistics, and model the area dependency. The paper outlines the structures tested, and the thermal and field acceleration factors generated for different area sizes. It also outlines the reason for the area dependence and indicates how existing models must be modified to account for this dependency when predicting product reliability. The area analysis was conducted on flat P-type capacitors and on some NMOS structures to increase the area spread being investigated. The capacitors and transistors were fabricated on a 0.6 /spl mu/m dual poly dual metal CMOS process with a target deposited oxide thickness of 125 /spl Aring/. The process had been extensively characterized and monitored since release and all monitored lots showed only an intrinsic distribution.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117289412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Isothermal versus standard wafer electromigration test for the characterization of metal systems 金属体系表征的等温与标准晶圆片电迁移试验
D. Brisbin, T. Turner
{"title":"Isothermal versus standard wafer electromigration test for the characterization of metal systems","authors":"D. Brisbin, T. Turner","doi":"10.1109/IRWS.1997.660308","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660308","url":null,"abstract":"The isothermal electromigration test has recently been introduced as a potential alternative to the SWEAT technique. In the isothermal test, the stress current is adjusted in a feedback loop so that a constant metal line temperature is maintained. This differs from the SWEAT test, where the mean time to failure (MTF) as predicted by Black's equation is the control parameter. Once at the control temperature, the isothermal test can utilize three alternative stress modes: constant power, constant current or constant resistance (temperature). The isothermal test has several important advantages, including: (1) simplicity of implementation; (2) line temperature is directly controlled, so it is easier to avoid the bulk diffusion region; (3) algorithm does not require empirical adjustment of acceleration factors; (4) alternative stress modes are available to optimize performance. The purpose of this paper is to compare the isothermal and SWEAT tests experimentally in terms of MTF and standard deviation, and to evaluate the three different isothermal test modes of constant power, constant current or constant resistance.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127642751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Charge pumping for DRAM retention diagnostic 用于DRAM保留诊断的电荷泵送
J. Adkisson, R. Divakaruni, J. Slinkman
{"title":"Charge pumping for DRAM retention diagnostic","authors":"J. Adkisson, R. Divakaruni, J. Slinkman","doi":"10.1109/IRWS.1997.660295","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660295","url":null,"abstract":"Charge pumping is an effective technique used extensively to analyze the interface state density of submicron MOSFETs. In essence, charge pumping measures the interface state density by pulsing the gate between inversion and accumulation. By filling traps with minority carriers in the inversion portion of the pulse, and allowing the minority carriers to recombine with majority carriers during the accumulation portion of the pulse, a DC current is generated in the body of the device. The magnitude of the charge-pumping current is then proportional to the number of pulses and the interface state density. We describe the use of charge pumping to diagnose retention behavior of DRAM arrays. This allows in-situ testing of the DRAM array device and, therefore, direct correlation to charge-retention characteristics of the functional 16 Mb DRAM chip. The concept is extendible to any DRAM cell. Our goal here was to correlate the charge-pumping current with retention failures in a DRAM to provide another diagnostic technique for retention learning.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121869253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
HCI lifetime enhancement by double implanted S/D (DISD) of Nch MOSFET in 0.25 /spl mu/m CMOS technology 在0.25 /spl μ m CMOS技术下,Nch MOSFET双植入S/D (DISD)提高HCI寿命
D. Wu, S. Luning, D. Ju, N. Kepler
{"title":"HCI lifetime enhancement by double implanted S/D (DISD) of Nch MOSFET in 0.25 /spl mu/m CMOS technology","authors":"D. Wu, S. Luning, D. Ju, N. Kepler","doi":"10.1109/IRWS.1997.660280","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660280","url":null,"abstract":"The results of an intensive study of drain engineering work to improve the hot carrier injection (HCI) reliability of N-channel MOSFETs in 0.25 /spl mu/m CMOS technology are presented. While an As/P LDD structure improved HCI by sacrificing off-current, an alternative method of integrating phosphorus into the heavy dose As S/D junction delivers an equivalent HCI lifetime and an even lower off-current. Around one order of magnitude of HCI lifetime enhancement has been achieved with this P-doping of the S/D. Device simulations supported our approach.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130235112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Acceleration factors of PMOS hot carrier degradation PMOS热载流子降解的加速因子
H. Katto
{"title":"Acceleration factors of PMOS hot carrier degradation","authors":"H. Katto","doi":"10.1109/IRWS.1997.660274","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660274","url":null,"abstract":"The acceleration factors of hot carrier (HC) degradation are investigated in detail for scaled PMOSFETs. Extrapolated lifetimes under usage conditions are found to be much longer than might be expected from DC stress tests simply interpreted in a traditional manner. The new findings are: (1) the LOG(lifetime) depends on stress-V/sub D/ not by a factor 1/V/sub D/ as in NMOSFETs, but by 1/(|V/sub D/-V/sub 0/), where the constant V/sub 0/ is a weak function of stress-V/sub G/; (2) device parameters have different acceleration factors; /spl Sigma/I/sub ds/, which best represents inverter operation, degrades more slowly than V/sub T/ or I/sub ds/ (at V/sub cc//2) under usage condition; (3) the PMOSFET degradation can be slow for another reason: the release of trapped electrons from oxide back to the silicon (Brox et al, IEEE Trans. vol. ED-41, pp. 1184-1196, 1994).","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128564006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of electronic corrections on the thickness dependence of thin oxide reliability 电子校正对薄氧化物可靠性厚度依赖性的影响
G. Alers, A. Oates, D. Monroe, K. Krisch, B. Weir
{"title":"Effect of electronic corrections on the thickness dependence of thin oxide reliability","authors":"G. Alers, A. Oates, D. Monroe, K. Krisch, B. Weir","doi":"10.1109/IRWS.1997.660281","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660281","url":null,"abstract":"The thickness dependence of constant voltage lifetime tests for thin oxides in the range of 50-125 /spl Aring/ show an apparent factor of 100 enhancement in the lifetime of 50 /spl Aring/ oxides relative to the 125 /spl Aring/ oxides at a fixed electric field. However, when corrections are made for the distribution of electrons at the silicon interface, including depletion in the silicon and quantum-mechanical screening effects, then this apparent enhancement is reduced and all oxides have similar lifetimes at a fixed field. This rescaling of oxide reliability demonstrates the importance of accurate determination of the electric field and oxide voltage in thin oxides, and that oxide reliability is not significantly affected by thickness down to 50 /spl Aring/, depending only on field. We compare different techniques for determining the effective thickness using current-voltage or capacitance-voltage curves. We show that accurate estimates of the electric field can be obtained from integration of the capacitance-voltage relation of the capacitor. When electric fields are calculated using C-V curves, a consistent set of extrapolation parameters can be obtained for all thicknesses.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"364 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132791846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new technique to extract TDDB acceleration parameters from fast Q/sub bd/ tests 一种从快速Q/sub /测试中提取TDDB加速度参数的新技术
Y. Chen, J. Suehle, B. Shen, J. Bernstein, C. Messick, P. Chaparala
{"title":"A new technique to extract TDDB acceleration parameters from fast Q/sub bd/ tests","authors":"Y. Chen, J. Suehle, B. Shen, J. Bernstein, C. Messick, P. Chaparala","doi":"10.1109/IRWS.1997.660287","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660287","url":null,"abstract":"A new technique is proposed to extract long-term constant voltage stress time-dependent dielectric breakdown (TDDB) acceleration parameters from highly accelerated constant current injection breakdown tests. This is the first time that an accurate correlation of the highly accelerated breakdown tests to long-term TDDB tests has been presented.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117155190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The non-uniqueness of breakdown distributions in silicon oxides 硅氧化物中击穿分布的非唯一性
J. C. Jackson, O. Oralkan, T. Robinson, D. Dumin, G. Brown
{"title":"The non-uniqueness of breakdown distributions in silicon oxides","authors":"J. C. Jackson, O. Oralkan, T. Robinson, D. Dumin, G. Brown","doi":"10.1109/IRWS.1997.661871","DOIUrl":"https://doi.org/10.1109/IRWS.1997.661871","url":null,"abstract":"Time-dependent-dielectric-breakdown (TDDB) distributions obtained from oxides of the same physical geometry and stressed at the same electric field were found to shift to shorter times when the amount of energy available to flow through electric breakdowns was increased. This paper shows that TDDB distributions are nonunique and that for a breakdown model to accurately describe the reliability of an oxide during actual use conditions, the oxide thermal geometry must be taken into account. An accurate method of obtaining electric breakdown distributions is also presented which allows the use of smaller sample sizes to obtain time-dependent-electric-breakdown (TDEB) distributions which are similar to TDDB distributions.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128530638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Confirmation of a predictive process dependent model of oxide charging 氧化物充注的预测过程依赖模型的确认
J. F. Conley
{"title":"Confirmation of a predictive process dependent model of oxide charging","authors":"J. F. Conley","doi":"10.1109/IRWS.1997.660309","DOIUrl":"https://doi.org/10.1109/IRWS.1997.660309","url":null,"abstract":"Summary form only given. The concept of building in reliability (BIR) has been gaining attention in the semiconductor industry. Full realization of BIR, in our view, requires the development of physics-based models of the effects of process parameter variations on reliability mechanisms and subsequent incorporation of these models into predictive semiconductor TCAD tools. Previously, a physics-based model of charge trapping in \"intrinsic\" SiO/sub 2/ was introduced (Conley et al, IEEE Integrated Reliability Workshop Final Report, p. 134-141, 1996) and its potential predictive power demonstrated on a limited array of oxides (by \"intrinsic\", it is meant that trapping due to extrinsic contaminants is insignificant). Here, work is presented that confirms the validity of the model's parameters and shows that the model is predictive for a variety of oxides. In addition, very preliminary results are presented that address the equilibrium kinetics assumptions that were made in order to calibrate this model.","PeriodicalId":193522,"journal":{"name":"1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129171832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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