在0.25 /spl μ m CMOS技术下，Nch MOSFET双植入S/D (DISD)提高HCI寿命

1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI:10.1109/IRWS.1997.660280

D. Wu, S. Luning, D. Ju, N. Kepler

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引用次数: 0

摘要

本文介绍了在0.25 /spl μ m CMOS技术下，为提高n沟道mosfet热载流子注入(HCI)可靠性而进行的漏极工程研究的结果。虽然As/P LDD结构通过牺牲关断电流来改善HCI，但将磷集成到大剂量As S/D结中的另一种方法可以提供等效的HCI寿命和更低的关断电流。通过对S/D进行p掺杂，HCI寿命提高了约一个数量级。设备模拟支持我们的方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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HCI lifetime enhancement by double implanted S/D (DISD) of Nch MOSFET in 0.25 /spl mu/m CMOS technology

The results of an intensive study of drain engineering work to improve the hot carrier injection (HCI) reliability of N-channel MOSFETs in 0.25 /spl mu/m CMOS technology are presented. While an As/P LDD structure improved HCI by sacrificing off-current, an alternative method of integrating phosphorus into the heavy dose As S/D junction delivers an equivalent HCI lifetime and an even lower off-current. Around one order of magnitude of HCI lifetime enhancement has been achieved with this P-doping of the S/D. Device simulations supported our approach.

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来源期刊

1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)

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