HCI lifetime enhancement by double implanted S/D (DISD) of Nch MOSFET in 0.25 /spl mu/m CMOS technology

Abstract

The results of an intensive study of drain engineering work to improve the hot carrier injection (HCI) reliability of N-channel MOSFETs in 0.25 /spl mu/m CMOS technology are presented. While an As/P LDD structure improved HCI by sacrificing off-current, an alternative method of integrating phosphorus into the heavy dose As S/D junction delivers an equivalent HCI lifetime and an even lower off-current. Around one order of magnitude of HCI lifetime enhancement has been achieved with this P-doping of the S/D. Device simulations supported our approach.