A novel in-process wafer-level screening technique for CMOS devices

We have developed a novel in-process wafer-level screening technique to eliminate CMOS device infant mortality due to gate oxide defects. Using this technique, it is possible to stress all gate oxides simultaneously at an arbitrary high voltage for both n-channel and p-channel transistors. This paper describes the details of the screening method and its application to the standard 0.8 /spl mu/m CMOS logic technology. The result shows that early TDDB failures are significantly reduced by this technique.