设计期间开发的高性能CMOS逻辑技术将器件可靠性提高到0.13 /spl mu/m

1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319) Pub Date : 1997-10-13 DOI:10.1109/IRWS.1997.660279

D. Nayak, M. Hao, R. Hijab

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引用次数: 0

摘要

在先进CMOS工艺技术的发展过程中，每一代技术都在高性能和可靠性之间进行权衡。在这项工作中，我们提出了这些权衡，因为CMOS器件从0.5 /spl mu/m-generation缩放到0.13 /spl mu/m-generation技术。

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Designing-in device reliability during the development of high-performance CMOS logic technology to 0.13 /spl mu/m

During the development of advanced CMOS process technology, the trade-off between high performance and reliability is being made in each generation of technology. In this work, we present these trade-offs as the CMOS devices are scaled from 0.5 /spl mu/m-generation to 0.13 /spl mu/m-generation technology.

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来源期刊

1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)

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