C. Stolicny, Richard A. Davies, Pamela McKernan, Tuyen Truong
{"title":"Manufacturing pattern development for the Alpha 21164 microprocessor","authors":"C. Stolicny, Richard A. Davies, Pamela McKernan, Tuyen Truong","doi":"10.1109/TEST.1997.639628","DOIUrl":"https://doi.org/10.1109/TEST.1997.639628","url":null,"abstract":"Functional test patterns play a key role in the test strategy of many microprocessors. This paper describes the process of creating and fault grading an initial set of functional test vectors. The fault simulation results are used to identify design verification test (DVT) hard faults and to guide additional test development. Moreover, this paper details the effectiveness of test creation heuristics and the role functional tests play in identifying defective devices. This process has been used to improve the outgoing quality levels of Digital's second generation Alpha microprocessor.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"333 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122847741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A simulation-based JTAG ATPG optimized for MCMS","authors":"A. Flint","doi":"10.1109/TEST.1997.639600","DOIUrl":"https://doi.org/10.1109/TEST.1997.639600","url":null,"abstract":"Boundary scan test generation tools generate tests based on the netlist of the design. Netlist-based tools are very efficient in designs with a high percentage of boundary scan devices, but can be inefficient in designs containing a significant percentage of non-compatible ICs. An alternative method, in which the user defines the nets to test, is explored.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124824983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Testability features of AMD-K6/sup TM/ microprocessor","authors":"R. S. Fetherston, I. Shaik, Siyad C. Ma","doi":"10.1109/TEST.1997.639643","DOIUrl":"https://doi.org/10.1109/TEST.1997.639643","url":null,"abstract":"This paper describes the testability features and test pattern development methodologies for the AMD-K6/sup TM/ microprocessor. The embedded design for testability (DFT) structures and test strategy provide high quality manufacturing tests.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123647174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The case for partial scan","authors":"J. Rearick","doi":"10.1109/TEST.1997.639722","DOIUrl":"https://doi.org/10.1109/TEST.1997.639722","url":null,"abstract":"The full scan design methodology undisputably has many benefits throughout the process of ASIC and system design and during the life cycle of a product that may justify its use, but it has some very definite costs as well. These include larger die area, reduced circuit performance and the fact that there are usually a number of memory elements which are not scanned. It is suggested that partial scan be useful in augmenting the test coverage on critical portions of high performance chips, and that it can also serve as the basis for an area-efficient design methodology on any chip. Partial scan is another facet of the continual improvement process in IC design. As new developments in flip-flop selection and sequential ATPG are integrated into design flows, partial scan can become as push-button as full scan now is. When coupled with a design methodology driven by timing analysis and synthesis, partial scan could well be the key to producing designs that are optimized for performance, area, and testability.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125552538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ASIC manufacturing test cost prediction at early design stage","authors":"V. Kim, Tom Chen, Mick Tegethoff","doi":"10.1109/TEST.1997.639637","DOIUrl":"https://doi.org/10.1109/TEST.1997.639637","url":null,"abstract":"This paper proposes a rest cost prediction model which estimates the cost of lC testing in a manufacturing environment. The model predicts chip testing cost and quality of test using a set of circuit manufacturing parameters. The objective is to use these circuit parameters which are available at the early stage of the design cycle to determine and optimize manufacturing test cost.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129780430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A unified interface for scan test generation based on STIL","authors":"P. Wohl, J. Waicukauski","doi":"10.1109/TEST.1997.639718","DOIUrl":"https://doi.org/10.1109/TEST.1997.639718","url":null,"abstract":"The Standard Test Interface Language (STIL) was developed for universal pattern interchange form test generation tools output to tester input. We extend the usage of STIL to the various input files of a test generation tool we developed, thus using one language where traditional test tools use five or more. This significantly reduces engineering time to learn the required languages, create and maintain all files. The output STIL file generated contains the information from ail input files, eliminating the confusion often caused by managing multiple versions of multiple files. Users can start with only a minimal input file, have the tool fill in defaults, and write out a complete STIL file. This file can be modified and read back in as any of the input files, allowing stepwise refinements.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129226902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Memory test-debugging test vectors without ATE","authors":"Steve Westfall","doi":"10.1109/TEST.1997.639678","DOIUrl":"https://doi.org/10.1109/TEST.1997.639678","url":null,"abstract":"A method for debugging functional production test vectors for memory devices without the use of Automated Test Equipment (ATE) is presented. The method described involves the use of a digital simulation environment; a reactive Hardware Description Language (HDL) ATE model; and ATE rules checking. The method allows for rapidly debugging vectors and rest program flows without requiring the use of ATE resources.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128513491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Signature analysis for IC diagnosis and failure analysis","authors":"C. Henderson, J. Soden","doi":"10.1109/TEST.1997.639632","DOIUrl":"https://doi.org/10.1109/TEST.1997.639632","url":null,"abstract":"A method of signature analysis is presented that is based on ATE data, experiential knowledge of failure modes and mechanisms, or a combination of both. This method can be used on low numbers of failures or even single failures. It uses the Dempster-Shafer theory to calculate failure mechanism confidence. This method can be used for rapid diagnosis of complex IC failures. The model is developed and an example is given based on Sandia's 0.5 /spl mu/m CMOS IC technology.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128721260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Michael Mateja, A. Crouch, R. Eisele, G. Giles, Dale Amason
{"title":"A case study of the test development for the 2nd generation ColdFire/sup R/ microprocessors","authors":"Michael Mateja, A. Crouch, R. Eisele, G. Giles, Dale Amason","doi":"10.1109/TEST.1997.639645","DOIUrl":"https://doi.org/10.1109/TEST.1997.639645","url":null,"abstract":"A case study of the development of the design for test methodology of the second generation of the ColdFire/sup R/ Microprocessor Family is described from the viewpoint of goals, initial strategy and implementation. Methodology includes at-speed scan path design, path delay testing, I/sub DDQ/ and direct access test modes for embedded memories. Scan tests are applied with timing identical to that specified for peak performance normal operation.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121268217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Experiences with implementation of I/sub DDQ/ test for identification and automotive products","authors":"R. Arnold, Markus Feuser, H. Wedekind, T. Bode","doi":"10.1109/TEST.1997.639605","DOIUrl":"https://doi.org/10.1109/TEST.1997.639605","url":null,"abstract":"Quality improvements for CMOS devices by using I/sub DDQ//I/sub SSQ/ tests are a popular topic since early 1990s. This is a report about experiences with the implementation of novel I/sub DDQ/ test methods for Identification & Automotive products at Philips Semiconductors. The aim is to describe the considerations, quality assurance strategy and its realization for Identification & Automotive products like Smart Card Controller ICs for Chip Cards and Radio Frequency Transponders for contactless car immobilization systems considering special security requirements. The main issue of Philips quality strategy is to achieve a better overall quality without sacrificing device costs. In addition to the test aspects some organizational, design, library, Computer Aided Test software, production and other quality & reliability related issues are covered.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130799490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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