Michael Mateja, A. Crouch, R. Eisele, G. Giles, Dale Amason
{"title":"第二代ColdFire/sup R/微处理器测试开发案例研究","authors":"Michael Mateja, A. Crouch, R. Eisele, G. Giles, Dale Amason","doi":"10.1109/TEST.1997.639645","DOIUrl":null,"url":null,"abstract":"A case study of the development of the design for test methodology of the second generation of the ColdFire/sup R/ Microprocessor Family is described from the viewpoint of goals, initial strategy and implementation. Methodology includes at-speed scan path design, path delay testing, I/sub DDQ/ and direct access test modes for embedded memories. Scan tests are applied with timing identical to that specified for peak performance normal operation.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"A case study of the test development for the 2nd generation ColdFire/sup R/ microprocessors\",\"authors\":\"Michael Mateja, A. Crouch, R. Eisele, G. Giles, Dale Amason\",\"doi\":\"10.1109/TEST.1997.639645\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A case study of the development of the design for test methodology of the second generation of the ColdFire/sup R/ Microprocessor Family is described from the viewpoint of goals, initial strategy and implementation. Methodology includes at-speed scan path design, path delay testing, I/sub DDQ/ and direct access test modes for embedded memories. Scan tests are applied with timing identical to that specified for peak performance normal operation.\",\"PeriodicalId\":186340,\"journal\":{\"name\":\"Proceedings International Test Conference 1997\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Test Conference 1997\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1997.639645\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Test Conference 1997","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1997.639645","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A case study of the test development for the 2nd generation ColdFire/sup R/ microprocessors
A case study of the development of the design for test methodology of the second generation of the ColdFire/sup R/ Microprocessor Family is described from the viewpoint of goals, initial strategy and implementation. Methodology includes at-speed scan path design, path delay testing, I/sub DDQ/ and direct access test modes for embedded memories. Scan tests are applied with timing identical to that specified for peak performance normal operation.