Proceedings International Test Conference 1997最新文献

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Test access of TAP'ed and non-TAP'ed cores 测试TAP和非TAP芯线的访问
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639730
L. Whetsel
{"title":"Test access of TAP'ed and non-TAP'ed cores","authors":"L. Whetsel","doi":"10.1109/TEST.1997.639730","DOIUrl":"https://doi.org/10.1109/TEST.1997.639730","url":null,"abstract":"Core reuse is an emerging IC design style which enables rapid development of highly complex ICs. Reusable circuit cores come in two basic varieties, hard and soft. Hard cores are optimized for area and performance and are not modifiable by the user, whereas soft cores are user modifiable. If soft cores do not contain testability (i.e. scan/BIST), it can be inserted into the core by the user. Hard cores cannot have test features inserted by the user. Hard core providers should therefore include some means of testing the cores to prevent users from having to add testability external to the core, using pin access or scan/BIST collaring for example. In addition to the hard and soft core varieties, cores will be available for reuse with and without IEEE 1149.1 test access ports (TAPs). Non-TAP'ed cores are circuits that don't have the need for a TAP architecture. They may be scan or BIST testable via a simple, instruction-less test interface. Testable, non-TAP'ed cores could be viewed as 1149.1 test data registers that simply plug into an IC's boundary scan TAP domain to be accessed by TAP instructions. IC providers will face a dilemma when ICs contain two or more TAP domains. Various options for solving this dilemma are discussed.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115714212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Why would an ASIC foundry accept anything less than full scan? 为什么ASIC代工厂会接受不完全扫描的东西?
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639721
S. F. Oakland
{"title":"Why would an ASIC foundry accept anything less than full scan?","authors":"S. F. Oakland","doi":"10.1109/TEST.1997.639721","DOIUrl":"https://doi.org/10.1109/TEST.1997.639721","url":null,"abstract":"A key force behind IBM's growth in the application-specific integrated circuit (ASIC) market is the ability to sign off on multi-million-gate designs without requiring test vectors, presenting a savings in both time and money to customers. Once a customer ensures (via formal verification and/or functional simulation) that the design functions as required, static tinting analysis (STA) ensures that the design achieves the required performance targets. Extensive model-to-hardware correlation assures correctness of the timing analysis models, enabling IBM to assure that the design can be manufactured to the required performance targets. Through a combination of full-scan and boundary-scan design-for-test (DFT) structures, the IBM ASIC methodology ensures that automatically generated test patterns will run correctly on test equipment; typically achieving 99+% stuck-fault coverage. In the case of a repeatable manufacturing defect, full-scan-based diagnostic software isolates the problem without customer involvement.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125157889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Putting the squeeze on test sequences 对测试序列施加压力
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639685
E. Rudnick, J. Patel
{"title":"Putting the squeeze on test sequences","authors":"E. Rudnick, J. Patel","doi":"10.1109/TEST.1997.639685","DOIUrl":"https://doi.org/10.1109/TEST.1997.639685","url":null,"abstract":"Dynamic test sequence compaction is an effective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. A new algorithm for dynamic test sequence compaction is presented that uses genetic techniques to evolve test sequences. Test sequences provided by a test generator and previously evolved sequences already included in the test set are used as seeds in the genetic population. Significant improvements in test set size, fault coverage, and test generation time have been obtained over previous approaches.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125289353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Application and analysis of IDDQ diagnostic software IDDQ诊断软件的应用与分析
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639633
P. Nigh, D. Forlenza, F. Motika
{"title":"Application and analysis of IDDQ diagnostic software","authors":"P. Nigh, D. Forlenza, F. Motika","doi":"10.1109/TEST.1997.639633","DOIUrl":"https://doi.org/10.1109/TEST.1997.639633","url":null,"abstract":"A current disadvantage of IDDq testing is lack of software-based diagnostic tools that enable IC vendors to create a large database of defects uniquely detected with this test method. We present a methodology for performing defect localization based upon IDDq test information (only). Using this technique, fault localization can be completed within minutes (e.g. <5 minutes) after IC testing is complete. This technique supports multiple fault models and has been successfully applied to a large number of samples-including ones that have been verified through failure analysis. Data is presented related to key issues such as diagnostic resolution, hardware-to-fault model correlation, diagnostic current thresholds, and the diagnosability of various defect types.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122291402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Design and realization of an accurate built-in current sensor for on-line power dissipation measurement and I/sub DDQ/ testing 用于在线功耗测量和I/sub DDQ/测试的精确内置电流传感器的设计与实现
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639666
Karim Arabi, B. Kaminska
{"title":"Design and realization of an accurate built-in current sensor for on-line power dissipation measurement and I/sub DDQ/ testing","authors":"Karim Arabi, B. Kaminska","doi":"10.1109/TEST.1997.639666","DOIUrl":"https://doi.org/10.1109/TEST.1997.639666","url":null,"abstract":"Built-in current sensor (BICS) is known to enhance test accuracy, defect coverage and test rate of quiescent current (I/sub DDQ/) testing method in CMOS VLSI circuits. For new deep-submicron technologies, BICSs become essential for accurate and practical I/sub DDQ/ testing. This paper presents a new BICS suitable for on-line power dissipation measurement and I/sub DDQ/ testing. Although the BICS presented in this paper is dedicated to submicron technologies that require reduced supply voltage, it can also be used for applications and technologies requiring normal supply voltage. The proposed BICS has been extended for on-line measurement of the power dissipation using only an additional capacitor. Power dissipation measurement is important for safety-critical applications and battery-powered systems. A simple self-test approach to verify the functionality and accuracy of BICSs has also been introduced. The proposed BICS has been implemented and tested using an N-well CMOS 1.2 /spl mu/m technology. Practical results demonstrate that a very good measurement accuracy can be achieved.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127923857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
"Ethics, professionalism and accountability in testing" “考试中的道德、专业和问责”
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639724
W. Simpson
{"title":"\"Ethics, professionalism and accountability in testing\"","authors":"W. Simpson","doi":"10.1109/TEST.1997.639724","DOIUrl":"https://doi.org/10.1109/TEST.1997.639724","url":null,"abstract":"Testing is not an exact science. We can test for a class of anomalies, and certify a product does not contain those anomalies under test conditions. We can test for another class of anomalies under operational conditions, but it is never clear when the list is complete. The test engineer has to balance the conflicting requirements between customer's expectations, his boss' expectations, and market forces. If he fails in maintaining this balance, he fails at his job. However, there exists instances where ethics would dictate that a balance is impossible. The author discusses these problematic issues facing the test engineer.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131041501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Supervisors for testing non-deterministically specified systems 测试非确定性指定系统的监督员
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639710
T. Savor, R. Seviora
{"title":"Supervisors for testing non-deterministically specified systems","authors":"T. Savor, R. Seviora","doi":"10.1109/TEST.1997.639710","DOIUrl":"https://doi.org/10.1109/TEST.1997.639710","url":null,"abstract":"An approach to automate detection of behavioral failures during system testing is described. A supervisor monitors the inputs and outputs of a system under test. It reports discrepancies between observed and specified behaviors as failures. Failures due to both design and implementation are detectable. The approach presented is able to tolerate legal behavioral alternatives arising out of specification non-determinism.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128848741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Screening for known good die (KGD) based on defect clustering: an experimental study 基于缺陷聚类的已知好模(KGD)筛选的实验研究
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639638
A. Singh, P. Nigh, C. M. Krishna
{"title":"Screening for known good die (KGD) based on defect clustering: an experimental study","authors":"A. Singh, P. Nigh, C. M. Krishna","doi":"10.1109/TEST.1997.639638","DOIUrl":"https://doi.org/10.1109/TEST.1997.639638","url":null,"abstract":"Die screening based on the locality of defects has long been informally practised in the industry whereby dice from wafers, or parts of the wafer, that display high defect levels are discarded. More recently this approach has been refined such that test results for neighbouring dice on the wafer are also considered in evaluating test results for a particular die. It has been shown in principle, using negative binomial statistics for defect distributions on wafers, that such an approach can much better optimize test costs and screen for low defect levels in bare dice and packaged chips. In this paper we present, for the first time, experimental test data to demonstrate the effectiveness of this new approach. Our results are based on extensive testing of 4784 dice on 23 wafers from an IBM process. We show that bare die screening based on defect clustering considerations can significantly reduce defect levels in dice that pass wafer probe tests. This approach also has the potential to screen out burn-in failures. Thus it offers new low cost strategies for delivering high quality \"known- good\" die (KGD) for MCM applications.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127073349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Incorporating physical design-for-test into routing 将物理测试设计纳入路由
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639681
R. McGowen, F. Ferguson
{"title":"Incorporating physical design-for-test into routing","authors":"R. McGowen, F. Ferguson","doi":"10.1109/TEST.1997.639681","DOIUrl":"https://doi.org/10.1109/TEST.1997.639681","url":null,"abstract":"In addition to automatically generating correct wiring, routers are used to meet additional design goals. Examples include reducing capacitive coupling and improving yield. Using routers to improve testability has been mentioned in the literature, but concrete rules or methods have not been explained or implemented. In this paper, we show how a modified router improves bridge fault testability for two different test metrics, static-voltage testing and pseudo-exhaustive segmentation testing, with no significant increase in area or time. This method is flexible in that further testability improvements are possible by trading off routing area or routing time.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115119255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On-line testing for VLSI VLSI在线测试
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639731
M. Nicolaidis
{"title":"On-line testing for VLSI","authors":"M. Nicolaidis","doi":"10.1109/TEST.1997.639731","DOIUrl":"https://doi.org/10.1109/TEST.1997.639731","url":null,"abstract":"A large variety of on-line testing techniques for VLSI was developed in the past and are still enriched by new developments. They can respond efficiently to the increasing complexity of VLSI circuits under the condition that available CAD tools simplify their implementation. Amongst the advanced online testing techniques are: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test, ...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components, radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"92 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123437724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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