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Proceedings International Test Conference 1997最新文献

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Test width compression for built-in self testing 测试宽度压缩内置自检
Proceedings International Test Conference 1997 Pub Date : 1997-11-01 DOI: 10.1109/TEST.1997.639634
K. Chakrabarty, Jian Liu, Minyao Zhu, B. Murray
{"title":"Test width compression for built-in self testing","authors":"K. Chakrabarty, Jian Liu, Minyao Zhu, B. Murray","doi":"10.1109/TEST.1997.639634","DOIUrl":"https://doi.org/10.1109/TEST.1997.639634","url":null,"abstract":"We present a method for designing test generator circuits (TGCs) that incorporate a precomputed test set to in the patterns they produce. Our method uses width compression based on the property of d-compatibles, which allows us to encode to more efficiently than previous methods that use only compatibles and inverse compatibles. The TGC consists of a counter, which generates a set of encoded test patterns, and a decompression circuit consisting of simple binary decoders that generate a final sequence containing T/sub D/. These TGCs are applicable to embedded-core circuits whose detailed designs are not available. We demonstrate the effectiveness of our approach by presenting experimental results for the ISCAS 85 and ISCAS CAS 89 benchmark circuits.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128153220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Algorithms for switch level delay fault simulation 开关级延迟故障仿真算法
Proceedings International Test Conference 1997 Pub Date : 1997-11-01 DOI: 10.1109/TEST.1997.639714
S. Bose, V. Agrawal, T. G. Szymanski
{"title":"Algorithms for switch level delay fault simulation","authors":"S. Bose, V. Agrawal, T. G. Szymanski","doi":"10.1109/TEST.1997.639714","DOIUrl":"https://doi.org/10.1109/TEST.1997.639714","url":null,"abstract":"Delay test problems are well understood for gate level circuits. For certain logic families, delays depend on the charge stored at internal nodes. For such circuits, gate level models do not surface, A switch level simulator can be used for logic verification and stuck-at fault simulation. Toward making the delay fault simulation possible, this paper contributes three innovations to the switch-level technique: (1) Signals that remain steady over two consecutive vectors are identified using additional strength designations for charge and discharge paths; (2) Delay faults are propagated through MOS gates using articulation analyse's of the graph; and (3) A modified relaxation procedure determines the steady or non-steady status of signals at the same time it evaluates nodes. Experimental results demonstrate the validity of algorithms.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132823336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Scan latch design for delay test 延迟测试扫描锁存器设计
Proceedings International Test Conference 1997 Pub Date : 1997-11-01 DOI: 10.1109/TEST.1997.639650
J. Savir
{"title":"Scan latch design for delay test","authors":"J. Savir","doi":"10.1109/TEST.1997.639650","DOIUrl":"https://doi.org/10.1109/TEST.1997.639650","url":null,"abstract":"This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting one of the new SRLs are reported on three pilot chips.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115349003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Fault macromodeling for analog/mixed-signal circuits 模拟/混合信号电路的故障宏建模
Proceedings International Test Conference 1997 Pub Date : 1997-11-01 DOI: 10.1109/TEST.1997.639706
Chen-Yang Pan, K. Cheng
{"title":"Fault macromodeling for analog/mixed-signal circuits","authors":"Chen-Yang Pan, K. Cheng","doi":"10.1109/TEST.1997.639706","DOIUrl":"https://doi.org/10.1109/TEST.1997.639706","url":null,"abstract":"In this paper we propose an efficient fault macromodeling technique for analog/mixed-signal circuits. We formulate the fault macromodeling problem as a problem of deriving the macro parameter set B based on the performance parameter set P of the transistor-level faulty circuit. The fault macromodel is intended to be used for efficient macro-level fault simulation. In such applications, a common approach to speeding up the macromodeling process is to generate a large number of data pairs (P, B) (the training set) and interpolate an empirical mapping function B=F(P) based on the training set. In our technique, generation of each data pair requires only one run of macro-level simulation, as opposed to multiple runs of macro-level simulation required by iterative fault macromodeling techniques. We also propose a cross-correlation-based technique to select a subset of parameters from the high dimensional parameter set P to speed up function interpolation. We demonstrate the effectiveness and efficiency of our proposed fault macromodeling technique by showing some preliminary, experimental results on an industrial design.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127176804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
The implementation of pseudo-random memory tests on commercial memory testers 在商用内存测试器上实现伪随机内存测试
Proceedings International Test Conference 1997 Pub Date : 1997-11-01 DOI: 10.1109/TEST.1997.639618
A. V. Goor, Mike Lin
{"title":"The implementation of pseudo-random memory tests on commercial memory testers","authors":"A. V. Goor, Mike Lin","doi":"10.1109/TEST.1997.639618","DOIUrl":"https://doi.org/10.1109/TEST.1997.639618","url":null,"abstract":"The increasing emphasis on reducing the defect level of shipped memory parts demands very high fault coverage of memory tests. Deterministic tests have the advantage of 100% fault coverage for the targeted (i.e., anticipated) faults. However, with each new technology, new layout and new fab process, new types of defects will show up; the probability of occurrence of these defects is not known before production start and, in addition, may vary during the time period the parts are produced. Pseudo-random (PR) memory tests are tests which have the capability to detect any fault (defect) of any model; albeit with some probability less than 100%; the fault coverage is modular and depends on the test time, which makes them very attractive. However, problems arise when commercial testers have to be used for applying PR tests. This paper illustrates these problems and shows how they can be overcome. The results are applicable to a large class of commercial memory testers thereby making them useable for PR memory tests.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114786224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
I/sub DDQ/ characterization in submicron CMOS 亚微米CMOS中的I/sub DDQ/表征
Proceedings International Test Conference 1997 Pub Date : 1997-11-01 DOI: 10.1109/TEST.1997.639606
A. Ferré, J. Figueras
{"title":"I/sub DDQ/ characterization in submicron CMOS","authors":"A. Ferré, J. Figueras","doi":"10.1109/TEST.1997.639606","DOIUrl":"https://doi.org/10.1109/TEST.1997.639606","url":null,"abstract":"The effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and non-defective quiescent currents. Consequently, the interest in characterizing these currents is growing. In this paper we focus our attention on the non-defective I/sub DDQ/ current characterization. The dependence of I/sub DDQ/ on the channel length spread in scaled down devices is examined. The I/sub DDQ/ distribution of a subthreshold current dominant technology is obtained. Finally, I/sub DDQ/ test limits depending on acceptable yield loss and standard deviation of the channel length are determined.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114162442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Hardware compression speeds on bitmap fail display 位图显示失败时的硬件压缩速度
Proceedings International Test Conference 1997 Pub Date : 1997-11-01 DOI: 10.1109/TEST.1997.639598
R. Gage, B. Brown, John Donaldson, Alexander Joffe
{"title":"Hardware compression speeds on bitmap fail display","authors":"R. Gage, B. Brown, John Donaldson, Alexander Joffe","doi":"10.1109/TEST.1997.639598","DOIUrl":"https://doi.org/10.1109/TEST.1997.639598","url":null,"abstract":"A unique lossless data compression algorithm has been implemented into a Bitmap Display Processor. This scanner hardware will allow massive non-lossy compression of bitmap failure images on the order of 10000 to one. The capability should allow new opportunities for testing speed and qualities, with small file sizes and fast image updates.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124082986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ErrorTracer: a fault simulation-based approach to design error diagnosis ErrorTracer:基于故障模拟的设计错误诊断方法
Proceedings International Test Conference 1997 Pub Date : 1997-11-01 DOI: 10.1109/TEST.1997.639713
Shi-Yu Huang, K. Cheng, Kuang-Chien Chen, D. I. Cheng
{"title":"ErrorTracer: a fault simulation-based approach to design error diagnosis","authors":"Shi-Yu Huang, K. Cheng, Kuang-Chien Chen, D. I. Cheng","doi":"10.1109/TEST.1997.639713","DOIUrl":"https://doi.org/10.1109/TEST.1997.639713","url":null,"abstract":"This paper addresses the problem of locating error sources in an erroneous combinational circuit. We use a fault simulation-based technique to approximate each signal's correcting power. The correcting power of a particular signal is measured in terms of the signal's correctable set, namely, the maximum set of erroneous input vectors that can be corrected by re-synthesizing the signal. Only the signals that can correct every erroneous input vector are considered as a potential error source. Our algorithm offers three major advantages over existing methods. First, unlike symbolic approaches, it is applicable for large circuits. Secondly, it delivers more accurate results than other simulation-based approaches because it is based on a more stringent condition for identifying potential error sources. Thirdly, it can be easily generalized to identify multiple errors. Experimental results on diagnosing circuits with one and two random errors are presented to show the effectiveness and efficiency of this new approach.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129008084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Scan synthesis for one-hot signals 单热信号的扫描合成
Proceedings International Test Conference 1997 Pub Date : 1997-11-01 DOI: 10.1109/TEST.1997.639684
S. Mitra, L. Avra, E. McCluskey
{"title":"Scan synthesis for one-hot signals","authors":"S. Mitra, L. Avra, E. McCluskey","doi":"10.1109/TEST.1997.639684","DOIUrl":"https://doi.org/10.1109/TEST.1997.639684","url":null,"abstract":"Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot signals. In a scan-based design, one-hot values on these signals may not be maintained during the scan-in and scan-out operations. Also, the presence of faults, the existence of don't care conditions and the use of random patterns for testing the circuit in a scan or BIST environment may lead to non-one-hot values on these one hot signals, resulting in abnormal circuit behavior and possible circuit damage. In this paper, we present new techniques for synthesizing scan-based designs so that one-hot values are maintained on the one-hot signals during all modes of operation. One of our synthesis techniques often generates designs with no area overhead-the designs are smaller than those that do not ensure safe scan operation. In addition, we propose a scan path design that has no performance overhead during the normal mode of operation and ensures that only valid states appear on the bistables during test mode, thus guaranteeing safe scan operations.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129300888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Test requirements for embedded core-based systems and IEEE P1500 基于嵌入式核心系统和IEEE P1500的测试要求
Proceedings International Test Conference 1997 Pub Date : 1997-11-01 DOI: 10.1109/TEST.1997.639613
Y. Zorian
{"title":"Test requirements for embedded core-based systems and IEEE P1500","authors":"Y. Zorian","doi":"10.1109/TEST.1997.639613","DOIUrl":"https://doi.org/10.1109/TEST.1997.639613","url":null,"abstract":"Chips comprising reusable cores, i.e. pre-designed Intellectual Property (IP) blocks, have become an important part of IC-based system design. Using embedded cores enables the design of high-complexity system-chips with densities as high as millions of gates on a single die. The increase in using pre-designed IP cores in system-chips adds to the complexity of test. To test system-chips adequately, test solutions need to be incorporated into individual cores and then the tests from individual cores need to be scheduled and assembled into a chip level test. However with the increased usage of cores from multiple and diverse sources, it is essential to create standard mechanisms to make core test plug-and-play possible. This paper discusses in general the challenges in testing core-based system-chips and describes their corresponding test solutions. It concentrates on the common test requirements and introduces the on-going standardization efforts, specifically under IEEE P1500 Working Group, which is meant to standardize the interface between a core test and its host the System-on-Chip.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132714160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 138
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