I/sub DDQ/ characterization in submicron CMOS

Abstract

The effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and non-defective quiescent currents. Consequently, the interest in characterizing these currents is growing. In this paper we focus our attention on the non-defective I/sub DDQ/ current characterization. The dependence of I/sub DDQ/ on the channel length spread in scaled down devices is examined. The I/sub DDQ/ distribution of a subthreshold current dominant technology is obtained. Finally, I/sub DDQ/ test limits depending on acceptable yield loss and standard deviation of the channel length are determined.