The implementation of pseudo-random memory tests on commercial memory testers

Abstract

The increasing emphasis on reducing the defect level of shipped memory parts demands very high fault coverage of memory tests. Deterministic tests have the advantage of 100% fault coverage for the targeted (i.e., anticipated) faults. However, with each new technology, new layout and new fab process, new types of defects will show up; the probability of occurrence of these defects is not known before production start and, in addition, may vary during the time period the parts are produced. Pseudo-random (PR) memory tests are tests which have the capability to detect any fault (defect) of any model; albeit with some probability less than 100%; the fault coverage is modular and depends on the test time, which makes them very attractive. However, problems arise when commercial testers have to be used for applying PR tests. This paper illustrates these problems and shows how they can be overcome. The results are applicable to a large class of commercial memory testers thereby making them useable for PR memory tests.