{"title":"Pentium(R) Pro processor design for test and debug","authors":"Adrian Carbine, D. Feltham","doi":"10.1109/TEST.1997.639630","DOIUrl":"https://doi.org/10.1109/TEST.1997.639630","url":null,"abstract":"This paper describes the Design for Test (DFT) and silicon debug features of the Pentium(R) Pro processor, and its production test development methodology. The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led the design team to a custom low-area DFT approach, coupled with a manually-written test methodology which targeted several fault models. Results show that this approach was effective in balancing testability needs with other design constraints, while enabling excellent time to market and test quality.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133453553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low current and low voltages-the high-end op amp testing challenge","authors":"Bob Cometta, J. Witte","doi":"10.1109/TEST.1997.639693","DOIUrl":"https://doi.org/10.1109/TEST.1997.639693","url":null,"abstract":"State-of-the-art op amps with input bias currents in the fA range and offset voltages of several /spl mu/V present special test problems. The authors discuss the measurement problems and their possible solutions. The topics discussed include: DSP based input bias current measurement; leakage current compensation; and current loop feedback.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133214340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The application of novel failure analysis techniques for advanced multi-layered CMOS devices","authors":"Yeoh Eng Hong, M. We","doi":"10.1109/TEST.1997.639631","DOIUrl":"https://doi.org/10.1109/TEST.1997.639631","url":null,"abstract":"The major focus of this paper is on innovative fault localisation approaches that make use of DFT (design for testability) features, fanin tree, assembly code programming and functional model simulation as FA tools. Besides these, defect localisation techniques and revolutionary backside FA techniques are discussed. All these tools enhance FA activities and increase the chance of defect detection. Without these tools, FA on extremely complex devices such as microprocessors will be extremely difficult, if not impossible.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128924985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takahiro J. Yamaguchi, M. Ishida, M. Tilgner, D. Ha
{"title":"An efficient method for compressing test data","authors":"Takahiro J. Yamaguchi, M. Ishida, M. Tilgner, D. Ha","doi":"10.1109/TEST.1997.639597","DOIUrl":"https://doi.org/10.1109/TEST.1997.639597","url":null,"abstract":"The overall throughput of automatic test equipment (ATE) is sensitive to the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. A compression algorithm for test data should meet two requirements: lossless and simple decompression. In this paper we propose a new test data compression method that aims to fully utilize the unique characteristics of test data compression. The key idea of the proposed method is to perform the Burrows-Wheeler transformation on the sequence of test patterns, and then to apply run-length coding. The experimental results show that our compression method performs better than six other methods for compressing test data. The average compression ratio of the proposed method performed on five test data sets is 315, while that for the next best one, the LZW method, is 21.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116971910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Pin margin analysis","authors":"R. E. Huston","doi":"10.1109/TEST.1997.639677","DOIUrl":"https://doi.org/10.1109/TEST.1997.639677","url":null,"abstract":"A method and tool is described to increase test program standards and lower program maintenance cost through Pin Margin Analysis. Exposure of DUT and ATE characteristics during test program operation will lead to maximizing test margins.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124777665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Development of a MEMS testing methodology","authors":"A. Kolpekwar, R. D. Blanton","doi":"10.1109/TEST.1997.639707","DOIUrl":"https://doi.org/10.1109/TEST.1997.639707","url":null,"abstract":"Microelectromechanical systems (MEMS) are miniature electromechanical sensor and actuator systems developed from the mature batch-fabricated processes of VLSI technologies. Projected growth in the MEMS market requires significant advances in CAD and manufacturing for MEMS. These advances must be accompanied with testing methodologies that ensure both high quality and reliability. We describe our approach for developing a comprehensive testing methodology for a class of MEMS known as surface micromachined sensors. Our first step involving manufacturing process and low-level mechanical simulations is illustrated by studying the effects of realistic contaminations on the folded-flexure comb-drive resonator. The simulation results obtained indicate that realistic contaminations can create a variety of defective structures that result in a wide spectrum of faulty behaviors.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129640347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Testability analysis and ATPG on behavioral RT-level VHDL","authors":"Fulvio Corno, P. Prinetto, M. Reorda","doi":"10.1109/TEST.1997.639688","DOIUrl":"https://doi.org/10.1109/TEST.1997.639688","url":null,"abstract":"This paper proposes an environment to address testability analysis and test pattern generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on an abstract representation, is particularly suited for large circuits, where gate-level ATPGs are often inefficient.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124517304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ACT: a DFT tool for self-timed circuits","authors":"A. Khoche, E. Brunvand","doi":"10.1109/TEST.1997.639697","DOIUrl":"https://doi.org/10.1109/TEST.1997.639697","url":null,"abstract":"This paper presents a Design for Testability (DFT) tool called ACT (Asynchronous Circuit Testing) which uses a partial scan technique to make macro-module based self-timed circuits testable. The ACT tool is the first of its kind for testing macro-module based self-timed circuits. ACT modifies designs automatically to incorporate partial scan and provides a complete path from schematic capture to physical layout. It also has a test generation system to generate vectors for the testable design and to compute fault coverage of the generated tests. The test generation system includes a module for doing critical hazard free test generation using a new 6-valued algebra. ACT has been built around commercial tools from Viewlogic and Cascade. A Viewlogic schematic is used as the design entry point and Cascade tools are used for technology mapping.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116313673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Kaminska, Karim Arabi, I. Bell, J. Huertas, B. Kim, A. Rueda, M. Soma, P. Goteti
{"title":"Analog and mixed-signal benchmark circuits-first release","authors":"B. Kaminska, Karim Arabi, I. Bell, J. Huertas, B. Kim, A. Rueda, M. Soma, P. Goteti","doi":"10.1109/TEST.1997.639612","DOIUrl":"https://doi.org/10.1109/TEST.1997.639612","url":null,"abstract":"The IEEE Mixed-Signal Technical Activity Committee is developing a common set of benchmark circuits for use in researching and evaluating analog fault modeling, test generation, design-for-test, and built-in self-test methodologies. The first release circuits are based on MITEL Semiconductor's 1.5 /spl mu/m and 1.2 /spl mu/m CMOS technologies and they will allow engineers and researchers working in analog and mixed-signal testing to compare test results as is done in the digital domain. This paper presents a set of typical circuits described by netlists in HSPICE format. Schematic diagrams, simulation results and measured results, if available, are provided together with layout and a typical test environment. The full details are available on the web page dedicated to analog and mixed-signal benchmarks.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126467650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"DS-LFSR: a new BIST TPG for low heat dissipation","authors":"Seongmoon Wang, S. Gupta","doi":"10.1109/TEST.1997.639699","DOIUrl":"https://doi.org/10.1109/TEST.1997.639699","url":null,"abstract":"A test pattern generator (TPG) for built-in self-test (BIST), which can reduce heat dissipation during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS-LFSR), consists of two linear feedback shift registers (LFSRs), a slow LFSR and a normal-speed LFSR. The slow LFSR is driven by a slow clock whose speed is width that of the normal clock which drives the normal-speed LFSR, The use of DS-LFSR lowers the transition density at the circuit inputs driven by the slow LFSR, leading to a reduction in heat dissipation during test application. A procedure is presented to design a DS-LFSR so as to achieve high fault coverage by ensuring that patterns generated by it are unique and uniformly distributed. A new gain function, and a method to compute its value for each circuit input, is proposed to select inputs to be driven by the slow LFSR. Also, a procedure to increase the number of inputs driven by the slow LFSR by combining compatible inputs is presented to further decrease the heat dissipation, Finally, DS-LFSRs are designed for the ISCAS85 and ISCAS89 benchmark circuits and shown to provide 13% to 70% reduction in the numbers of transitions with no loss of fault coverage and at very slight area overheads.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126871694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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