DS-LFSR: a new BIST TPG for low heat dissipation

Abstract

A test pattern generator (TPG) for built-in self-test (BIST), which can reduce heat dissipation during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS-LFSR), consists of two linear feedback shift registers (LFSRs), a slow LFSR and a normal-speed LFSR. The slow LFSR is driven by a slow clock whose speed is width that of the normal clock which drives the normal-speed LFSR, The use of DS-LFSR lowers the transition density at the circuit inputs driven by the slow LFSR, leading to a reduction in heat dissipation during test application. A procedure is presented to design a DS-LFSR so as to achieve high fault coverage by ensuring that patterns generated by it are unique and uniformly distributed. A new gain function, and a method to compute its value for each circuit input, is proposed to select inputs to be driven by the slow LFSR. Also, a procedure to increase the number of inputs driven by the slow LFSR by combining compatible inputs is presented to further decrease the heat dissipation, Finally, DS-LFSRs are designed for the ISCAS85 and ISCAS89 benchmark circuits and shown to provide 13% to 70% reduction in the numbers of transitions with no loss of fault coverage and at very slight area overheads.