{"title":"新型失效分析技术在先进多层CMOS器件中的应用","authors":"Yeoh Eng Hong, M. We","doi":"10.1109/TEST.1997.639631","DOIUrl":null,"url":null,"abstract":"The major focus of this paper is on innovative fault localisation approaches that make use of DFT (design for testability) features, fanin tree, assembly code programming and functional model simulation as FA tools. Besides these, defect localisation techniques and revolutionary backside FA techniques are discussed. All these tools enhance FA activities and increase the chance of defect detection. Without these tools, FA on extremely complex devices such as microprocessors will be extremely difficult, if not impossible.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"The application of novel failure analysis techniques for advanced multi-layered CMOS devices\",\"authors\":\"Yeoh Eng Hong, M. We\",\"doi\":\"10.1109/TEST.1997.639631\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The major focus of this paper is on innovative fault localisation approaches that make use of DFT (design for testability) features, fanin tree, assembly code programming and functional model simulation as FA tools. Besides these, defect localisation techniques and revolutionary backside FA techniques are discussed. All these tools enhance FA activities and increase the chance of defect detection. Without these tools, FA on extremely complex devices such as microprocessors will be extremely difficult, if not impossible.\",\"PeriodicalId\":186340,\"journal\":{\"name\":\"Proceedings International Test Conference 1997\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Test Conference 1997\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1997.639631\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Test Conference 1997","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1997.639631","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The application of novel failure analysis techniques for advanced multi-layered CMOS devices
The major focus of this paper is on innovative fault localisation approaches that make use of DFT (design for testability) features, fanin tree, assembly code programming and functional model simulation as FA tools. Besides these, defect localisation techniques and revolutionary backside FA techniques are discussed. All these tools enhance FA activities and increase the chance of defect detection. Without these tools, FA on extremely complex devices such as microprocessors will be extremely difficult, if not impossible.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
