{"title":"Tree-structured linear cellular automata and their applications as PRPGs","authors":"J. Li, X. Sun, K. Soon","doi":"10.1109/TEST.1997.639700","DOIUrl":"https://doi.org/10.1109/TEST.1997.639700","url":null,"abstract":"This paper introduces a family of pseudorandom test pattern generators, named tree-structured linear cellular automata (TLCA). The empirical study on the ISCAS'85 benchmark circuits shows the effectiveness of TLCA for testing sequential faults.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117287077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Addressing early design-for-test synthesis in a production environment","authors":"V. Chickermane, K. Zarrineh","doi":"10.1109/TEST.1997.639620","DOIUrl":"https://doi.org/10.1109/TEST.1997.639620","url":null,"abstract":"The maturity of high-level synthesis systems has enabled the use of design-for-test (DFT) methods early in the design phase. Early DFT synthesis ensures that the processing and transformation of multibit register variables, clock-gating, and initialization specifications are consistent with the high-level specification. Functional and test logic can be optimized in the same pass without the need for an iterative timing closure procedure. It allows designers to keep a single design source while synthesizing and mapping the logic to multiple technology libraries. This paper addresses the implementation of an early DFT synthesis system and presents experimental results to compare the early mode insertion approach with a late-mode approach.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125406823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault model extension for diagnosing custom cell fails","authors":"G. Vandling, Thomas Bartenstein","doi":"10.1109/TEST.1997.639670","DOIUrl":"https://doi.org/10.1109/TEST.1997.639670","url":null,"abstract":"This paper describes an extension of the standard, stuck-at fault model typically used for diagnostics. By defining stuck-at faults at all levels of a design hierarchy, diagnostic simulation has been able to succinctly identify a number of custom circuit design and modeling errors. Approximately half of these errors were not well identified by conventional diagnostics.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126815139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Diagnosis of bridging faults in sequential circuits using adaptive simulation, state storage, and path-tracing","authors":"S. Venkataraman, W. Fuchs","doi":"10.1109/TEST.1997.639702","DOIUrl":"https://doi.org/10.1109/TEST.1997.639702","url":null,"abstract":"A diagnosis technique that integrates the storage of precomputed information with some dynamic computation for the diagnosis of bridging faults in synchronous sequential circuits with no-scan or partial-scan is presented. The method addresses the accuracy, storage requirements, and computational complexity required for diagnosis. A combination of adaptively simulating the behavior of a bridging fault and storing faulty state information at select vectors ensures accuracy with low storage requirements. The combination of adaptive simulation, state storage, and pathtracing has low computational requirements. Experimental results are provided for the ISCAS89 benchmark circuits.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122161826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Voorakaranam, S. Chakrabarti, J. Hou, A. Gomes, S. Cherubal, A. Chatterjee, W. Kao
{"title":"Hierarchical specification-driven analog fault modeling for efficient fault simulation and diagnosis","authors":"R. Voorakaranam, S. Chakrabarti, J. Hou, A. Gomes, S. Cherubal, A. Chatterjee, W. Kao","doi":"10.1109/TEST.1997.639705","DOIUrl":"https://doi.org/10.1109/TEST.1997.639705","url":null,"abstract":"In this paper we discuss the capabilities of the MiST PROFIT (Mixed Signal Test Program for Fault Insertion and Testing) software for hierarchical fault modeling, tolerance modeling, fault clustering and fault diagnosis of complex mixed-signal systems. The software is designed to exploit the relationships between high level system specifications and module-level faults in complex and nonlinear mixed signal systems. Hierarchical simulation based methods are used to capture fault effects at different levels of circuit abstraction. The key features of our approach are: (a) the ability to compute tolerance effects from nonlinear behavioral models at different levels of circuit design hierarchy accurately using low-cost simulation based methods, (b) the ability to perform compaction of fault effects while transferring fault effects from the leaf cells to the highest level behavioral models, (c) the ability to capture parametric (soft) failure effects over the entire anticipated range of faulty parameter values and (d) the ability to construct fault dictionaries given a set of least replaceable units to diagnose.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130436264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Why automate optical inspection?","authors":"D. Raymond, Dominic F. Haigh","doi":"10.1109/TEST.1997.639723","DOIUrl":"https://doi.org/10.1109/TEST.1997.639723","url":null,"abstract":"It is suggested that automated optical inspection (AOI) competes effectively to fill the in-circuit test gap. AOI adds no unwelcome technologies to the workplace. Its programming and its results are simple and understandable in visual terms. AOI is thus considered high in strength, simplicity and universality. It is expected to grow rapidly, driven by the never ending demand for strong, simple, universal inspection methods.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124607652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Beasley, S. Pour-Mozafari, D. Huggett, A. Righter, C. J. Apodaca
{"title":"i/sub DD/ pulse response testing applied to complex CMOS ICs","authors":"J. Beasley, S. Pour-Mozafari, D. Huggett, A. Righter, C. J. Apodaca","doi":"10.1109/TEST.1997.639591","DOIUrl":"https://doi.org/10.1109/TEST.1997.639591","url":null,"abstract":"This paper presents test results for detecting defects in complex ICs by analyzing the changes observed in the power-on transient power supply currents for the IC. This test technique, called i/sub DD/ pulse response testing simultaneously pulses the V/sub DD/ and V/sub SS/ power supply rails while applying a fixed midrange bias voltage to all inputs to the DUT. The resulting power on transient current signature is then analyzed for the presence of abnormal behavior. Two methods of analyzing the transient current signature waveform are compared for two types of complex CMOS ICs. The type of defects detected by the test as well as applications of this method to production test are discussed.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133946701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-performance production test contactors for fine-pitch integrated circuit","authors":"James J. Brandes","doi":"10.1109/TEST.1997.639658","DOIUrl":"https://doi.org/10.1109/TEST.1997.639658","url":null,"abstract":"This paper describes the design of two contactors intended for testing fine-pitch BGA devices, specifically 0.75 mm and 0.5 mm pitches. The design emphasis is on high performance and high-volume production. The devices described provide superior electrical performance while being subjected to the rigors of production test. The paper describes the electrical and mechanical requirements of the contactors and quantifies these requirements. The contactor designs are then described individually. Finally, the design verification tests that ensure conformance to requirements are described.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129820368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A symbolic simulation-based ANSI/IEEE Std 1149.1 compliance checker and BSDL generator","authors":"Harbinder Singh, James Beausang, Girish Patankar","doi":"10.1109/TEST.1997.639621","DOIUrl":"https://doi.org/10.1109/TEST.1997.639621","url":null,"abstract":"The paper shows how to extract the boundary-scan circuitry from an IC (Integrated Circuit), verify its compliance to IEEE Std 1149.1 and generate its BSDL (Boundary Scan Description Language) description. This work applies to the 75% of boundary-scan ICs that have hand-generated or macro-cell based boundary-scan circuity. It also applies to boundary-scan ICs designed using RTL (Register Transfer Level) synthesis.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114828209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using BIST control for pattern generation","authors":"G. Kiefer, H. Wunderlich","doi":"10.1109/TEST.1997.639636","DOIUrl":"https://doi.org/10.1109/TEST.1997.639636","url":null,"abstract":"A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least. Hence, pattern counters and bit counters are always available, and they provide information to be used for deterministic pattern generation by some additional circuitry. This paper presents a systematic way for synthesizing a pattern generator which needs less area than a 32-bit LFSR for random pattern generation for all the benchmark circuits.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116464203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}