基于符号仿真的ANSI/IEEE Std 1149.1符合性检查器和BSDL生成器

Proceedings International Test Conference 1997 Pub Date : 1997-11-01 DOI:10.1109/TEST.1997.639621

Harbinder Singh, James Beausang, Girish Patankar

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引用次数: 9

摘要

本文介绍了如何从集成电路中提取边界扫描电路，验证其符合IEEE标准1149.1，并生成其边界扫描描述语言(BSDL)描述。这项工作适用于75%的具有手工生成或基于宏单元的边界扫描电路的边界扫描ic。它也适用于使用RTL(寄存器传输电平)合成设计的边界扫描ic。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A symbolic simulation-based ANSI/IEEE Std 1149.1 compliance checker and BSDL generator

The paper shows how to extract the boundary-scan circuitry from an IC (Integrated Circuit), verify its compliance to IEEE Std 1149.1 and generate its BSDL (Boundary Scan Description Language) description. This work applies to the 75% of boundary-scan ICs that have hand-generated or macro-cell based boundary-scan circuity. It also applies to boundary-scan ICs designed using RTL (Register Transfer Level) synthesis.

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Proceedings International Test Conference 1997

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