Addressing early design-for-test synthesis in a production environment

Abstract

The maturity of high-level synthesis systems has enabled the use of design-for-test (DFT) methods early in the design phase. Early DFT synthesis ensures that the processing and transformation of multibit register variables, clock-gating, and initialization specifications are consistent with the high-level specification. Functional and test logic can be optimized in the same pass without the need for an iterative timing closure procedure. It allows designers to keep a single design source while synthesizing and mapping the logic to multiple technology libraries. This paper addresses the implementation of an early DFT synthesis system and presents experimental results to compare the early mode insertion approach with a late-mode approach.