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Proceedings International Test Conference 1997最新文献

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Finding opens with optics 发现从光学开始
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639627
D. Raymond
{"title":"Finding opens with optics","authors":"D. Raymond","doi":"10.1109/TEST.1997.639627","DOIUrl":"https://doi.org/10.1109/TEST.1997.639627","url":null,"abstract":"As circuit densities continue their increase, Automated Optical Inspection (AOI) augments traditional test methods for assuring quality of electronic assemblies. AOI is particularly helpful in assembly lines where both sides of a board are reflowed. This most modern style of construction leads to products of unprecedented density, but also brings us difficulties with in-circuit fixturing. The loss of in-circuit fixturing has the potential to bring us products of greater cost and inferior quality. AOI offerings exist for several process steps, but by far the largest use of AOI is after solder reflow. AOI cannot eliminate all in-circuit test, but often fills the gaps left by the access deficit. AOI is also combined with flying probers and with functional testers. It is automated, and it is in the process. This is the runway on which AOI technology is gathering speed for takeoff, ultimately to become the primary choice for manufacturing inspection.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128227108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
BART: a bridging fault test generator for sequential circuits BART：顺序电路桥接故障测试生成器
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639698
J. Cusey, J. Patel
{"title":"BART: a bridging fault test generator for sequential circuits","authors":"J. Cusey, J. Patel","doi":"10.1109/TEST.1997.639698","DOIUrl":"https://doi.org/10.1109/TEST.1997.639698","url":null,"abstract":"The need for test generation tools which target bridging faults in addition to stuck-at faults is growing. This work introduces BART, a new bridging-fault-targeted test; generator based upon HITEC and E-PROOFS, and gauges its performance against that of other techniques for bridging fault testing. A new circuit modification is proposed which allows a single bridging fault to be represented as a collection of four stuck-at faults. This modification is refined so that lines can be justified so as to maximize the probability that the voltage on one of the bridged nodes is corrupted enough to represent an incorrect logic value. This refinement uses the concept of \"strong\" and \"weak\" logic values, which gauge the resistance of the path between a gate output and the driving rail. BART was able to produce test sets which gave reasonable coverage for sequential circuits as well as combinational circuits.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127148244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits 用于模拟和混合信号集成电路功能和结构测试的振荡内置自检(OBIST)方案
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639692
Karim Arabi, B. Kaminska
{"title":"Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits","authors":"Karim Arabi, B. Kaminska","doi":"10.1109/TEST.1997.639692","DOIUrl":"https://doi.org/10.1109/TEST.1997.639692","url":null,"abstract":"This paper describes a new built-in self test (BIST) technique suitable for both functional and structural testing of analog and mixed-signal circuits based on the oscillation-test methodology. Analog-to-digital converter (ADC) is used as a test vehicle to demonstrate the capability of the proposed OBIST technique for both functional and structural testing. Design of different parts of OBIST structure is also presented. The ADC conversion rate, differential nonlinearity (DNL) and integral nonlinearity (INL) at each quantization band edge (QBE) are tested as functional parameters. These parameters are considered to be the most important functional characteristics of an ADC. Practical experimentation using real-world successive approximation and flash ADCs confirms the accuracy of OBIST for functional testing of ADCs. Simulation results using a 3-bit flash ADC designed using a CMOS 1.2 /spl mu/m technology are also presented. For structural testing, oversampled sigma-delta ADCs are investigated. Both hard and soft faults are considered and some simulation results are presented.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115580943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 134
Analog AC harmonic method for detecting solder opens 模拟交流谐波方法检测焊点开孔
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639604
Chuck Robinson
{"title":"Analog AC harmonic method for detecting solder opens","authors":"Chuck Robinson","doi":"10.1109/TEST.1997.639604","DOIUrl":"https://doi.org/10.1109/TEST.1997.639604","url":null,"abstract":"Vectorless test techniques are attractive methods to quickly and inexpensively identify and diagnose common process related defects on manufacturers printed wiring boards. Junction Xpress is a new AC method developed to locate open and marginal solder connections without the use of digital vectors or overclamp style capacitive probes. Measuring response harmonics rather than simply the fundamental AC response reduces the tendency of false accepts of open connections.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128871918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Signal generation using periodic single and multi-bit sigma-delta modulated streams 信号生成使用周期单和多比特σ - δ调制流
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639642
B. Dufort, G. Roberts
{"title":"Signal generation using periodic single and multi-bit sigma-delta modulated streams","authors":"B. Dufort, G. Roberts","doi":"10.1109/TEST.1997.639642","DOIUrl":"https://doi.org/10.1109/TEST.1997.639642","url":null,"abstract":"This paper describes a new method to generate analog signals with high precision at very low hardware complexity. This method consists in reproducing periodically a recorded portion of the bitstream output of a sigma-delta modulate. This technique utilizes less hardware than conventional frequency synthesis methods and does not require a multi-bit DAC. However when a multi-bit DAC is already available, the technique can be used to increase the quality of the signal in the frequency band of interest using existing hardware. The paper demonstrates how this method can be used to generate signals for Built-in Self-Test and standard Analog and Mixed-Signal Test. Experimental results illustrating the design simplicity and low overhead are given.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127060933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
An effective BIST scheme for arithmetic logic units 一种有效的算术逻辑单元的BIST格式
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639701
D. Gizopoulos, A. Paschalis, Y. Zorian, M. Psarakis
{"title":"An effective BIST scheme for arithmetic logic units","authors":"D. Gizopoulos, A. Paschalis, Y. Zorian, M. Psarakis","doi":"10.1109/TEST.1997.639701","DOIUrl":"https://doi.org/10.1109/TEST.1997.639701","url":null,"abstract":"Multifunction arithmetic logic units (ALUs) that realize complex arithmetic and logic operations (like the operations of the 74/spl times/181 family) are widely used in today's complex integrated circuits, such as commercial microprocessors and digital signal processors. These ALUs are built around either ripple-carry (RC) adders, carry-lookahead (CLA) adders or mixed CLA/RC adders depending on area and performance requirements. In this paper, first, we introduce novel C-testable multifunction ALUs built around RC adders and linear-testable multifunction ALUs built around CLA adders and mined CLA/RC adders with respect to CFM. Then, we introduce an effective ALU BIST scheme for all three types of ALUs (RC, CLA, mixed CLA/RC) that hits the target of a unified datapath BIST architecture, since it is compatible to an effective BIST scheme for datapaths. Complete CFM testability is achieved with a reasonable number of deterministic test patterns in all cases. The scheme imposes reasonable area overhead and negligible delay overhead and owing to its inherent high regularity can be easily adopted for automatic BIST synthesis of datapaths.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122908185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
To DFT or not to DFT? 用DFT还是不用DFT?
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639664
S. Wei, P. Nag, R. D. Blanton, A. Gattiker, W. Maly
{"title":"To DFT or not to DFT?","authors":"S. Wei, P. Nag, R. D. Blanton, A. Gattiker, W. Maly","doi":"10.1109/TEST.1997.639664","DOIUrl":"https://doi.org/10.1109/TEST.1997.639664","url":null,"abstract":"Despite a substantial amount of prior work in design-for-testability (DFT) cost modeling, the decision whether or not and how to use DFT is still not an easy one. The problem is that the relationship between DFT benefits and costs are still far from being well understood. The objective of this paper is to study the DFT decision-making process and to identify its missing or weak links. The first step of this study involved development of a new DFT cost/benefit trade-off modeling procedure. Next, the developed cost model (which we call the CMU Test Cost model) was used, with a range of parameters representing typical industrial conditions, to answer the question: to DFT or not to DFT. The obtained results indicate that in the DFT application space there exist regions in which one can provide a clear answer to this question. There also exist regions of uncertainty. One of the objectives of our study has been to identify ways of minimizing this uncertain region.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123771820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Intrinsic leakage in low power deep submicron CMOS ICs 低功耗深亚微米CMOS集成电路的内禀泄漏
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639607
A. Keshavarzi, K. Roy, C. Hawkins
{"title":"Intrinsic leakage in low power deep submicron CMOS ICs","authors":"A. Keshavarzi, K. Roy, C. Hawkins","doi":"10.1109/TEST.1997.639607","DOIUrl":"https://doi.org/10.1109/TEST.1997.639607","url":null,"abstract":"The large leakage currents in deep submicron transistors threaten future products and established quality manufacturing techniques. These include the ability to manufacture low power and battery operated products, and the ability to perform I/sub DDQ/ sensitive measurements with the significant ensuing benefits to test, reliability, and failure analysis. This paper reports transistor intrinsic leakage reduction as functions of bias point, temperature, source-well backbiasing, and lowered power supply (V/sub DD/). These device properties are applied to a test application that combines I/sub DDQ/ and F/sub MAX/ to establish a 2-parameter limit for distinguishing intrinsic and extrinsic (defect) leakages in microprocessors with high background I/sub DDQ/ leakage.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121817188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 239
Identification of defective CMOS devices using correlation and regression analysis of frequency domain transient signal data 利用频域瞬态信号数据的相关和回归分析识别缺陷CMOS器件
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639592
J. Plusquellic, D. Chiarulli, S. Levitan
{"title":"Identification of defective CMOS devices using correlation and regression analysis of frequency domain transient signal data","authors":"J. Plusquellic, D. Chiarulli, S. Levitan","doi":"10.1109/TEST.1997.639592","DOIUrl":"https://doi.org/10.1109/TEST.1997.639592","url":null,"abstract":"Transient signal analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points and on I/sub DD/ switching transients on the supply rails. We show that it is possible to identify defective devices by analyzing the transient signals produced at test points on paths not sensitized from the defect site. The small signal variations produced at these test points are analyzed in the frequency domain. Correlation analysis shows a high degree of correlation in these signals across the outputs of defect-free devices. We use regression analysis to show the absence of correlation across the outputs of bridging and open drain defective devices.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131366888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Cell signal measurement for high-density DRAMs 高密度dram的蜂窝信号测量
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639616
J. Vollrath
{"title":"Cell signal measurement for high-density DRAMs","authors":"J. Vollrath","doi":"10.1109/TEST.1997.639616","DOIUrl":"https://doi.org/10.1109/TEST.1997.639616","url":null,"abstract":"Important parameters for scaling high-density DRAMs are the cell signal of each memory cell and the signal level applied to the sense amplifier during sensing. Moreover, failing memory cells need to be 'characterized' before a physical failure analysis can be carried out in order to determine the root causes of likely problems. It is common practice to put small pads on the bit lines (BLs) and probe the bit-line signal with so-called pico-probes. This paper describes a new approach to measuring the cell signal using a normal test procedure without pico-probes. Measurements determine the cell signal, BL, word line (WL) and isolator coupling.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1052 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116282903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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