BART:顺序电路桥接故障测试生成器

J. Cusey, J. Patel
{"title":"BART:顺序电路桥接故障测试生成器","authors":"J. Cusey, J. Patel","doi":"10.1109/TEST.1997.639698","DOIUrl":null,"url":null,"abstract":"The need for test generation tools which target bridging faults in addition to stuck-at faults is growing. This work introduces BART, a new bridging-fault-targeted test; generator based upon HITEC and E-PROOFS, and gauges its performance against that of other techniques for bridging fault testing. A new circuit modification is proposed which allows a single bridging fault to be represented as a collection of four stuck-at faults. This modification is refined so that lines can be justified so as to maximize the probability that the voltage on one of the bridged nodes is corrupted enough to represent an incorrect logic value. This refinement uses the concept of \"strong\" and \"weak\" logic values, which gauge the resistance of the path between a gate output and the driving rail. BART was able to produce test sets which gave reasonable coverage for sequential circuits as well as combinational circuits.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"BART: a bridging fault test generator for sequential circuits\",\"authors\":\"J. Cusey, J. Patel\",\"doi\":\"10.1109/TEST.1997.639698\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The need for test generation tools which target bridging faults in addition to stuck-at faults is growing. This work introduces BART, a new bridging-fault-targeted test; generator based upon HITEC and E-PROOFS, and gauges its performance against that of other techniques for bridging fault testing. A new circuit modification is proposed which allows a single bridging fault to be represented as a collection of four stuck-at faults. This modification is refined so that lines can be justified so as to maximize the probability that the voltage on one of the bridged nodes is corrupted enough to represent an incorrect logic value. This refinement uses the concept of \\\"strong\\\" and \\\"weak\\\" logic values, which gauge the resistance of the path between a gate output and the driving rail. BART was able to produce test sets which gave reasonable coverage for sequential circuits as well as combinational circuits.\",\"PeriodicalId\":186340,\"journal\":{\"name\":\"Proceedings International Test Conference 1997\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Test Conference 1997\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1997.639698\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Test Conference 1997","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1997.639698","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18

摘要

除卡滞故障外,针对桥接故障的测试生成工具的需求也在不断增长。这项研究介绍了基于 HITEC 和 E-PROOFS 的新型桥接故障目标测试生成器 BART,并将其性能与其他桥接故障测试技术进行了比较。提出了一种新的电路修改方法,可将单个桥接故障表示为四个卡住故障的集合。对这一修改进行了改进,使线路的合理性得以提高,从而最大限度地提高桥接节点之一上的电压被破坏到足以表示不正确逻辑值的概率。这一改进使用了 "强 "和 "弱 "逻辑值的概念,即测量栅极输出与驱动轨之间路径的电阻。BART 能够生成测试集,为顺序电路和组合电路提供合理的覆盖范围。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
BART: a bridging fault test generator for sequential circuits
The need for test generation tools which target bridging faults in addition to stuck-at faults is growing. This work introduces BART, a new bridging-fault-targeted test; generator based upon HITEC and E-PROOFS, and gauges its performance against that of other techniques for bridging fault testing. A new circuit modification is proposed which allows a single bridging fault to be represented as a collection of four stuck-at faults. This modification is refined so that lines can be justified so as to maximize the probability that the voltage on one of the bridged nodes is corrupted enough to represent an incorrect logic value. This refinement uses the concept of "strong" and "weak" logic values, which gauge the resistance of the path between a gate output and the driving rail. BART was able to produce test sets which gave reasonable coverage for sequential circuits as well as combinational circuits.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信