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Proceedings International Test Conference 1997最新文献

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IEEE P1149.4-almost a standard IEEE p1149.4——几乎是一个标准
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639611
A. Cron
{"title":"IEEE P1149.4-almost a standard","authors":"A. Cron","doi":"10.1109/TEST.1997.639611","DOIUrl":"https://doi.org/10.1109/TEST.1997.639611","url":null,"abstract":"The IEEE P1149.4 Mixed-Signal Test Bus Working Group is on the cusp of delivering a document that will finally standardize the architecture for, and the method of access to, the analog portion of mixed-signal circuits for test and diagnostic applications. This Standard will have the same profound effect on the design and test community that IEEE 1149.1 had previously. P1149.4 gives the test infrastructure the capability to measure discrete impedances external to devices supporting the Standard using a 6-wire bus. This bus uses 4 of the same signals used today to support 1149.1 compliant devices and subsystems. This paper will detail the basic architecture; give some design-specific information and data learned through the Standard's development process; relate results from several test devices; and provide a basic example of usage.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114633107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Effective path selection for delay fault testing of sequential circuits 时序电路延迟故障检测的有效路径选择
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639716
T. Chakraborty, V. Agrawal
{"title":"Effective path selection for delay fault testing of sequential circuits","authors":"T. Chakraborty, V. Agrawal","doi":"10.1109/TEST.1997.639716","DOIUrl":"https://doi.org/10.1109/TEST.1997.639716","url":null,"abstract":"This paper outlines several problems related to the delay fault testing of sequential circuits. For timing test of a circuit and for layout optimization, critical path data are needed. When critical paths are identified by a static timing analyzer many of the selected paths cannot be activated functionally. Such paths are sequential false paths. However, many of these paths can be activated and tested in the full or partial scan mode due to the increased controllability and observability. Therefore, it is possible that detection of a timing error on a sequential false path, when scan mode is used, can lead to the rejection of a functionally good circuit. We propose that these paths should not be targeted during delay test if scan mode is used. Similarly, sequential false paths should not be used for layout optimization or for selection of maximum clock rate. We present a novel algorithm to identify these paths. This algorithm is based on functional analysis of each target path for single and multiple path activation. If a path cannot be activated either way, it is sequentially false.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132166156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Parasitic effect removal for analog measurement in P1149.4 environment P1149.4环境下模拟测量的寄生效应去除
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639656
C. Su, Yue-Tsang Chen, S. Jou
{"title":"Parasitic effect removal for analog measurement in P1149.4 environment","authors":"C. Su, Yue-Tsang Chen, S. Jou","doi":"10.1109/TEST.1997.639656","DOIUrl":"https://doi.org/10.1109/TEST.1997.639656","url":null,"abstract":"An intrinsic response extraction algorithm is derived and implemented to remove the parasitic effects in P1149.4 analog measurement. The methodology is tested on and verified by SPICE simulation results and real measurement data.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122076097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Thoughts on core integration and test 关于核心集成和测试的思考
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639728
T. Anderson
{"title":"Thoughts on core integration and test","authors":"T. Anderson","doi":"10.1109/TEST.1997.639728","DOIUrl":"https://doi.org/10.1109/TEST.1997.639728","url":null,"abstract":"A number of initiatives have begun to address the integration and test of core-based chip design. Several organizations, including an IEEE Test Technology Technical Committee (TTTC) and working groups of the Virtual Socket Interface Alliance (VSIA), meet regularly to consider standards and solutions. The most immediate issue that a chip designer must face is the integration of a core (or cores) into the chip. Three main approaches are popular. FIFO-based interfaces are quite common for VO interconnect cores; they have simple protocol rules and mate up well with DMA designs in the application logic. The core might instead mate to a microprocessor or I/O bus. For example, a multi-function chip can use an on-chip PCI bus to connect together multiple cores with PCI interfaces. The final common approach is a bus defined explicitly by an ASIC vendor or core provider to interconnect cores. For all three types of core interconnection, handling functional operation is only half of the solution. As with all semiconductor devices, a core-based chip must be well tested in production to become a viable product.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124075763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
How seriously do you take possible-detect faults? 你对可能检测到的故障有多重视?
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639696
R. Raina, C. Njinda, R. Molyneaux
{"title":"How seriously do you take possible-detect faults?","authors":"R. Raina, C. Njinda, R. Molyneaux","doi":"10.1109/TEST.1997.639696","DOIUrl":"https://doi.org/10.1109/TEST.1997.639696","url":null,"abstract":"Digital designs, implemented in CMOS technology, have increasingly used tri-state logic (pass gates) to increase clock speed. It is also known that tri-state logic based designs have poor testability, as measured by the single stuck-at fault model, due to the proliferation of \"possible-detect\" faults. Design for test techniques that have been developed to address testability issues with tri-state logic designs, often incur hardware and cycle-time overheads. In this paper, we discuss the effect of one class of \"possible-detect\" faults and the implicit ability of a test pattern set in detecting such faults on real hardware.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127151264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Testing the enterprise IBM System/390/sup TM/ multi processor 测试企业IBM System/390/sup TM/多处理器
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639602
O. Torreiter, U. Baur, G. Goecke, K. Melocco
{"title":"Testing the enterprise IBM System/390/sup TM/ multi processor","authors":"O. Torreiter, U. Baur, G. Goecke, K. Melocco","doi":"10.1109/TEST.1997.639602","DOIUrl":"https://doi.org/10.1109/TEST.1997.639602","url":null,"abstract":"This paper describes the test generation strategies, novel test generation techniques and the tester strategy for testing the IBM System/390/sup TM/ Generation-3 Enterprise System Multi-Processor Module. The paper provides a review of the key test methodologies and a review of actual test results as seen at the product tester.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122427272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A simplified polynomial-fitting algorithm for DAC and ADC BIST 一种用于DAC和ADC的简化多项式拟合算法
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639641
S. Sunter, N. Nagi
{"title":"A simplified polynomial-fitting algorithm for DAC and ADC BIST","authors":"S. Sunter, N. Nagi","doi":"10.1109/TEST.1997.639641","DOIUrl":"https://doi.org/10.1109/TEST.1997.639641","url":null,"abstract":"An accurate and simple method is introduced for determining the third order polynomial that best fits a set of data points containing random noise. The coefficients of the polynomial are translated into offset, gain, and harmonic distortion for an analog-to-digital converter (ADC) driven by a digital-to-analog converter (DAC) or other appropriate signal source. The algorithm is efficient enough to be implemented as a built-in self-test for an IC, and is particularly suitable for sigma-delta converters.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117084281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 167
An on-line self-testing switched-current integrator 一种在线自检开关电流积分器
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639652
Osama K. Abu-Shahla, I. Bell
{"title":"An on-line self-testing switched-current integrator","authors":"Osama K. Abu-Shahla, I. Bell","doi":"10.1109/TEST.1997.639652","DOIUrl":"https://doi.org/10.1109/TEST.1997.639652","url":null,"abstract":"We describe a CMOS on-line-self-testing, double-sampled, fully-balanced, switched-current bilinear integrator. High spot-defect fault coverage of the integrator, clock generator and checking circuit is achieved under normal process variations.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114632170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Implementation of mixed current/voltage testing using the IEEE P1149.4 infrastructure 使用IEEE P1149.4基础架构实现混合电流/电压测试
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639657
J. M. D. Silva, A. C. Leão, J. S. Matos, J. Alves
{"title":"Implementation of mixed current/voltage testing using the IEEE P1149.4 infrastructure","authors":"J. M. D. Silva, A. C. Leão, J. S. Matos, J. Alves","doi":"10.1109/TEST.1997.639657","DOIUrl":"https://doi.org/10.1109/TEST.1997.639657","url":null,"abstract":"The development of a mixed-signal test bus infrastructure-IEEE P1149.4-is now in the final stages of the standardization process. Evaluating the test capabilities enabled by this infrastructure is an important step needed to support it as a well established standard. This paper presents experiments carried out with a test chip provided by the P1149.4 working group, which explore the architecture of the proposed analog boundary module to implement alternative testing methods. These include a method for parametric testing of passive components based on the monitoring of the power supply current, and a mixed current/voltage technique allowing the implementation of correlation for testing analog and mixed-signal macros.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121961829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Testability enhancement for behavioral descriptions containing conditional statements 增强了包含条件语句的行为描述的可测试性
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639619
Kelly A. Ockunzzi, C. Papachristou
{"title":"Testability enhancement for behavioral descriptions containing conditional statements","authors":"Kelly A. Ockunzzi, C. Papachristou","doi":"10.1109/TEST.1997.639619","DOIUrl":"https://doi.org/10.1109/TEST.1997.639619","url":null,"abstract":"A high-level test synthesis methodology based on BIST is proposed. This methodology targets the conditional if-then-else statements in a behavioral description because such statements can introduce testability problems in the resulting circuit. How well the operations in each branch of a conditional statement can be tested depends on the probability of taking each branch and the quality of the test patterns used in each branch. Behavioral modifications are presented that can resolve these testability issues. Experimental results from three practical examples show that this technique is effective.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130902512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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