Effective path selection for delay fault testing of sequential circuits

Abstract

This paper outlines several problems related to the delay fault testing of sequential circuits. For timing test of a circuit and for layout optimization, critical path data are needed. When critical paths are identified by a static timing analyzer many of the selected paths cannot be activated functionally. Such paths are sequential false paths. However, many of these paths can be activated and tested in the full or partial scan mode due to the increased controllability and observability. Therefore, it is possible that detection of a timing error on a sequential false path, when scan mode is used, can lead to the rejection of a functionally good circuit. We propose that these paths should not be targeted during delay test if scan mode is used. Similarly, sequential false paths should not be used for layout optimization or for selection of maximum clock rate. We present a novel algorithm to identify these paths. This algorithm is based on functional analysis of each target path for single and multiple path activation. If a path cannot be activated either way, it is sequentially false.