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Proceedings International Test Conference 1997最新文献

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HABIST: histogram-based analog built in self test HABIST:基于直方图的模拟内置自检
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639689
A. Frisch, T. Almy
{"title":"HABIST: histogram-based analog built in self test","authors":"A. Frisch, T. Almy","doi":"10.1109/TEST.1997.639689","DOIUrl":"https://doi.org/10.1109/TEST.1997.639689","url":null,"abstract":"This histogram based method of test collects a statistical representation of the activity at a node and processes that representation using a template histogram as a reference. In most cases, no special stimulus is required-data is collected in-situ, while the circuit under test is functioning. (Alternatively, analog stimulus, e.g. using a pseudo random sequence generator or stored digital vectors with a D to A converter, may be provided). The result of processing the data against the template histogram is a compressed human readable signature that defines gain, offset, noise, and distortion errors. These errors can then be used heuristically to determine causation. This paper describes the HABIST method and optional variations in its implementation, algorithms for processing histograms to obtain signatures and other compressed form of data, including waveform parameters, examples of the difference histograms that result from applying the algorithm, and methods and circuits for histogram generation.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"31 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132725496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Solder paste inspection: process control for defect reduction 锡膏检验:减少缺陷的过程控制
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639726
D. Burr
{"title":"Solder paste inspection: process control for defect reduction","authors":"D. Burr","doi":"10.1109/TEST.1997.639726","DOIUrl":"https://doi.org/10.1109/TEST.1997.639726","url":null,"abstract":"As quality control for SMT electronics assembly shifts from final inspection/final test to production line monitoring and process control, there is a greater emphasis on post-print solder paste inspection as a means of reducing the number of defects appearing on finished boards. Automatic post-print inspection systems provide operators with the continuous information required to implement in-line continuous process control, identifying out-of-spec trends so that printing problems can be corrected before defective boards are produced.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131672230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Oscillation and sequential behavior caused by interconnect opens in digital CMOS circuits 数字CMOS电路中互连打开引起的振荡和顺序行为
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639668
H. Konuk, F. Ferguson
{"title":"Oscillation and sequential behavior caused by interconnect opens in digital CMOS circuits","authors":"H. Konuk, F. Ferguson","doi":"10.1109/TEST.1997.639668","DOIUrl":"https://doi.org/10.1109/TEST.1997.639668","url":null,"abstract":"Shorts and opens are the most common types of defects in today's CMOS ICs. In this paper we show for the first time that an open in the interconnect wiring of a digital CMOS circuit can cause oscillation or sequential behavior. We also analyze and compare the factors affecting the probabilities for an interconnect open and a feedback bridging fault to oscillate or display sequential behavior.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114696007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Optical communication channel test using BIST approaches 使用BIST方法进行光通信信道测试
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639672
M. Gagnon, B. Kaminska
{"title":"Optical communication channel test using BIST approaches","authors":"M. Gagnon, B. Kaminska","doi":"10.1109/TEST.1997.639672","DOIUrl":"https://doi.org/10.1109/TEST.1997.639672","url":null,"abstract":"Novel Built-In Self-Test (BIST) approaches for integrated optoelectronic systems are presented The methods are compatible with scan chain design and allow testing the internal functionality of the device, the interconnection between modules, the analog characteristics of the transmitters and receivers and the Bit Error Rate (BER) of the channels. The proposed approaches enable system evaluation under realistic operating conditions (including crosstalk degradation) through BER testing. They can speedup both circuit-level and system-level testing by providing means for accessing different parts of the circuit easily and allowing time-consuming performance tests to be run in parallel with boundary-scan tests. Some preliminary experimental results are presented to confirm the proposed approaches for analog and mixed-signal methods.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132436674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An IEEE 1149.1 based test access architecture for ICs with embedded cores 基于IEEE 1149.1的嵌入式核心集成电路测试访问体系结构
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639596
L. Whetsel
{"title":"An IEEE 1149.1 based test access architecture for ICs with embedded cores","authors":"L. Whetsel","doi":"10.1109/TEST.1997.639596","DOIUrl":"https://doi.org/10.1109/TEST.1997.639596","url":null,"abstract":"This paper describes work at Texas Instruments regarding development of an IC architecture supporting hierarchical test access of embedded cores.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134019236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 125
On-line testing scheme for clock's faults 时钟故障在线检测方案
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639667
C. Metra, M. Favalli, B. Riccò
{"title":"On-line testing scheme for clock's faults","authors":"C. Metra, M. Favalli, B. Riccò","doi":"10.1109/TEST.1997.639667","DOIUrl":"https://doi.org/10.1109/TEST.1997.639667","url":null,"abstract":"This paper proposes an on-line testing scheme for permanent and temporary faults which affect signals of the clock distribution network of synchronous systems, and which make them stuck-at, or change with incorrect frequency or duty-cycle. By means of straightforward modifications, the proposed scheme can be also used to detect on-line undesired skews between couples of clock signals.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124617039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
So what is an optimal test mix? A discussion of the SEMATECH methods experiment 那么什么是最优的测试组合呢?SEMATECH方法实验的探讨
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639727
P. Nigh, W. Needham, K. Butler, Peter C. Maxwell, R. Aitken, Wojciech Maly
{"title":"So what is an optimal test mix? A discussion of the SEMATECH methods experiment","authors":"P. Nigh, W. Needham, K. Butler, Peter C. Maxwell, R. Aitken, Wojciech Maly","doi":"10.1109/TEST.1997.639727","DOIUrl":"https://doi.org/10.1109/TEST.1997.639727","url":null,"abstract":"The SEMATECH \"Test Methods Evaluation\" study, Project Number S-121, is an experiment to determine the relative merits of several test methodologies often used by SEMATECH member companies and other IC manufacturers. Conclusions drawn from the experiment thus far have indicated that each test methodology uniquely detects defects. This experimentation and analysis would not have been possible outside a consortium setting such as SEMATECH. Its conclusions may affect other major segments of the industry, including ATE manufacturers, CAD vendors, and academia. This paper gives a brief overview of the experiment and summarizes its findings.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115298777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 102
Logic diagnosis-diversion or necessity? 逻辑诊断——转移还是必要?
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639646
W. Fuch
{"title":"Logic diagnosis-diversion or necessity?","authors":"W. Fuch","doi":"10.1109/TEST.1997.639646","DOIUrl":"https://doi.org/10.1109/TEST.1997.639646","url":null,"abstract":"Failure diagnosis is resource intensive, frustrating, and often impossible. However, it is also critical and necessary for aggressive designs and manufacturing processes. Research in this area is making rapid progress, but the challenges are also rapidly growing in magnitude and importance.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116781348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Artificial intelligence exchange and service tie to all test environments (AI-ESTATE)-a new standard for system diagnostics 人工智能交换和服务连接到所有测试环境(AI-ESTATE)——系统诊断的新标准
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639719
J. Sheppard, L. Orlidge
{"title":"Artificial intelligence exchange and service tie to all test environments (AI-ESTATE)-a new standard for system diagnostics","authors":"J. Sheppard, L. Orlidge","doi":"10.1109/TEST.1997.639719","DOIUrl":"https://doi.org/10.1109/TEST.1997.639719","url":null,"abstract":"We describe a recently approved IEEE standard for exchanging diagnostic information and embedding diagnostic reasoners in any test environment. We describe the defined formats and services, an example application, and current industry acceptance.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121284421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Low cost ATE pin electronics for multigigabit-per-second at-speed test 低成本的ATE引脚电子器件，用于每秒千兆位的高速测试
Proceedings International Test Conference 1997 Pub Date : 1997-11-03 DOI: 10.1109/TEST.1997.639599
D. Keezer, R. Wenzel
{"title":"Low cost ATE pin electronics for multigigabit-per-second at-speed test","authors":"D. Keezer, R. Wenzel","doi":"10.1109/TEST.1997.639599","DOIUrl":"https://doi.org/10.1109/TEST.1997.639599","url":null,"abstract":"This paper describes the design and performance of low-cost electronics modules which can be used for testing multigigabit-per-second digital components and subsystems within an automated test environment. Pattern stimuli are generated at rates up to 2.67 Gbps with timing errors less than 50 ps. Pattern sensitivity is less than 40 ps and RMS jitter is typically about 8 ps. A high-speed differential buffer provides emitter-coupled logic (ECL) transitions in about 200 ps. A data-capture circuit is shown to sample repetitive waveforms with 2.67 Gbps data rates. It is estimated that the component cost per channel for a large ATE would be under $1000. Cost savings is achieved by eliminating unnecessary features, emphasizing simple yet precise design techniques, and use of commercially-available (low-cost) components.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129698942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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