{"title":"Modifying user-defined logic for test access to embedded cores","authors":"B. Pouya, N. Touba","doi":"10.1109/TEST.1997.639594","DOIUrl":"https://doi.org/10.1109/TEST.1997.639594","url":null,"abstract":"Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (UDL) surrounding the core may restrict the set of test vectors that can be applied to the core. Consequently, some of the core test vectors specified by the core supplier may not be contained in the output space of the UDL that drives the core and hence cannot be justified at the core inputs. Conventional solutions to this problem involve placing multiplexers or boundary scan elements at the inputs of the core to provide test access. This can be very costly in terms of area and performance. This paper presents a new approach for providing test access to an embedded core. A procedure is described for inserting control points in the UDL to modify its output space so that it contains the specified core test vectors. The flexibility in selecting the location of the control points is used to avoid performance degradation by keeping test logic off the critical timing paths. Experimental results are shown comparing the control point insertion procedure with other approaches.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130619701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analyzing a PowerPC/sup TM/ 620 microprocessor silicon failure using model checking","authors":"R. Raimi, J. Lear","doi":"10.1109/TEST.1997.639712","DOIUrl":"https://doi.org/10.1109/TEST.1997.639712","url":null,"abstract":"When silicon is available, newly designed microprocessors ore tested in specially equipped hardware laboratories, where real applications can be run at hardware speeds. However, the large volumes of code being run, plus the limited access to the internal nodes of the chip, make it extraordinarily difficult to characterize the nature of any failures that occur. In this paper, we describe how the formal verification technique of temporal logic model checking was used to quickly characterize a design error exhibited during hardware testing of the PowerPC 620 microprocessor. We claim that model checking can efficiently characterize such failures when certain pre-conditions are met. We also show how the same error could have been revealed early in the design cycle, by model checking a short and simple correctness specification. We discuss the implications of this for verification methodologies over the full design cycle.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131385701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Embedded at-speed test probe","authors":"Mitch Aigner","doi":"10.1109/TEST.1997.639708","DOIUrl":"https://doi.org/10.1109/TEST.1997.639708","url":null,"abstract":"The addition of a small analog probe circuit to an ASIC design allows previously unreachable internal signal nodes of the ASIC to be accurately monitored and measured with conventional test equipment. The probe is essentially a high-performance analog multiplexer, that can connect to up to 16 test points inside the core of the ASIC with minimal loading, and buffer these signals accurately to a transmission line driver output connected to a dedicated pad. A 0.65/spl mu/ CMOS implementation of the probe circuit provides a -3 dB bandwidth in excess of 400 MHz.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116572114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Test strategy sensitivity to defect parameters","authors":"M. Renovell, Y. Bertrand","doi":"10.1109/TEST.1997.639669","DOIUrl":"https://doi.org/10.1109/TEST.1997.639669","url":null,"abstract":"This paper demonstrates that the detection of defect depends on two classes of parameters: the predictable and unpredictable parameters. The demonstration is made with two very different types of defects (the interconnect short and the interconnect open) considering the static voltage, dynamic voltage and static current strategies. The value of the short resistance is the unpredictable parameter of the interconnect short and the polysilicon-to-bulk capacitance of the interconnect open. It is shown that any test strategy is able to detect shorts and opens each one for a given range of the unpredictable parameter called the 'analog detectability interval'. It is then demonstrated that the fundamental criterion for test strategy efficiency evaluation is the consideration of the analog detectability Intervals together with the unpredictable parameter distributions. It is finally shown that for realistic situations the voltage strategies exhibit a very good efficiency for a very reasonable cost making the use of expensive current strategy difficult to justify.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120946286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On using machine learning for logic BIST","authors":"C. Fagot, P. Girard, C. Landrault","doi":"10.1109/TEST.1997.639635","DOIUrl":"https://doi.org/10.1109/TEST.1997.639635","url":null,"abstract":"This paper presents a new approach for designing test sequences to be generated on-chip. The proposed technique is based on machine learning, and provides a way to generate efficient patterns to be used during BIST test pattern generation. The main idea is that test patterns detecting random pattern resistant faults are not embedded in a pseudo-random sequence as in existing techniques, but rather are used to produce relevant features allowing to generate directed random test patterns that detect random pattern resistant faults as well as easy-to-test faults. A BIST implementation that uses a classical LFSR plus a small amount of mapping logic is also proposed. Results are shown for benchmark circuits which indicate that our technique can reduce the weighted or pseudo-random test length required for a particular fault coverage. Other results are given to show the possible trade off between hardware overhead and test sequence length. An encouraging point is that results presented in this paper although they are comparable with those of existing mixed-mode techniques, have been obtained with a machine learning tool not specifically developed for BIST generation and therefore may significantly be improved.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127298813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"RF induction and analog junction techniques for finding opens","authors":"B. McElfresh","doi":"10.1109/TEST.1997.639624","DOIUrl":"https://doi.org/10.1109/TEST.1997.639624","url":null,"abstract":"In response to the need for fast and simple methods for detecting and diagnosing open pins on SMT devices, board test manufactures have introduced power-off, vectorless test techniques that provide reasonable fault coverage with little programming effort. This paper describes two techniques: the RF induction and the analog junction technique. The RF technique applies a 200-500kHz signal to a spiral loop antenna located over the device. This antenna or \"inducer\" produces an AC signals at the device pin under test which the in-circuit tester measures. The technique requires one inducer for each device to be tested. The test system software automatically learns the characteristics of the device being tested. The users need only describe the connections between the device and the tester, identify the device's power and ground pins, and which inducer is mounted over the part. The analog junction technique uses the device protection diodes. It requires no fixture hardware, relying only on the bed-of-nails contact with the device pins. The analog junction technique applies voltage to one pin of the device, causing current to flow between the pin and the device ground lead. Voltage is then applied another pin on the device, causing current to flow between this pin and the ground lead. Both the analog junction and RF induction techniques are effective means for detecting opens on digital devices.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122335597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The search for the universal probe card solution","authors":"R. Bates","doi":"10.1109/TEST.1997.639661","DOIUrl":"https://doi.org/10.1109/TEST.1997.639661","url":null,"abstract":"Epoxy Ring, Cobra, and other new products are evaluated against the demand for high pin count, high frequency, high temperature, multi-DUT, long life, etc. There doesn't appear to be a single universal solution, but rather each technology provides a usable response to the growing wafer test requirements. However, the climate is right for creativity and innovation to meet the challenges of the future.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129265095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault diagnosis in scan-based BIST","authors":"J. Rajski, J. Tyszer","doi":"10.1109/TEST.1997.639704","DOIUrl":"https://doi.org/10.1109/TEST.1997.639704","url":null,"abstract":"The paper presents a new fault diagnosis technique for scan-based BIST designs. It can be used for non-adaptive identification of the scan cells that are driven by erroneous signals, irrespective of the error multiplicity. The proposed scheme employs a simple scan cell selection hardware which in conjunction with a conventional signature analysis allows flexible tradeoffs between the test application time and the diagnostic resolution.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114855418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Experimental results for current-based analog scan","authors":"T. Bocek, T. Vu, M. Soma, Jason D. Moffatt","doi":"10.1109/TEST.1997.639690","DOIUrl":"https://doi.org/10.1109/TEST.1997.639690","url":null,"abstract":"This paper presents the design of current-mode circuits for analog scan, which include the highly accurate current-mirror scan latches and the analog shift registers. Experimental data from a test chip fabricated in Orbit 2-micron CMOS Foresight process illustrates that the accuracy of the circuits is sufficient for use in analog on-chip scan-based testing. The interface between analog scan and the P1149.4 test bus is discussed to show system-level applications of this technique.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130231100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. I. Cole, J. Soden, P. Tangyunyong, Patrick L. Candelaria, R. W. Beegle, D. Barton, C. Henderson, C. Hawkins
{"title":"Transient power supply voltage (V/sub DDT/) analysis for detecting IC defects","authors":"E. I. Cole, J. Soden, P. Tangyunyong, Patrick L. Candelaria, R. W. Beegle, D. Barton, C. Henderson, C. Hawkins","doi":"10.1109/TEST.1997.639590","DOIUrl":"https://doi.org/10.1109/TEST.1997.639590","url":null,"abstract":"Transient power supply voltage (V/sub DDT/) analysis is a new testing technique demonstrated as a powerful alternative and complement to I/sub DDQ/ testing. V/sub DDT/ analysis takes advantage of the limited response time of a voltage supply to the changing power demand of an IC during operation. Changes in the V/sub DD/ response time can be used to detect increases in the power demand of a microcontroller with resolutions of 20 nA at 100 kHz, 1 /spl mu/A at 1 MHz, and 2.5 /spl mu/A at 1.5 MHz. These current sensitivities have been shown for ICs with very low I/sub DDQ/ (<100 nA) and for an IC with an intrinsic I/sub DDQ/>300 /spl mu/A. The present system uses 100 cycle averaging to compensate for low frequency \"jitter\". The V/sub DDT/ signal acquisition protocols, frequency versus sensitivity tradeoffs, hardware considerations, noise limitations, data examples, and areas for future research are described.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127059173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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