{"title":"OLDEVDTP: a novel environment for off-line debugging of VLSI device test programs","authors":"Yuhai Ma, W. Shi","doi":"10.1109/TEST.1997.639680","DOIUrl":"https://doi.org/10.1109/TEST.1997.639680","url":null,"abstract":"Today's microelectronics researchers design VLSI devices to achieve highly differentiated devices, both in performance and functionality. As VLSI devices become more complex, VLSI device testing becomes more costly and time consuming. The increasing test complexity leads to longer device test programs development time as well as more expensive test systems, and debugging test programs is a great burden to the test programs development. This paper presents an off-line debugging environment, OLDEVDTP, for the creation, analysis, checking, identifying, error location, and correction of the device test programs off-line from the target VLSI test system, to achieve a dramatic cost and time reduction. Analysis, design, and implementation of OLDEVDTP are addressed in the paper.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115708614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Sequential test generation with advanced illegal state search","authors":"M. Konijnenburg, J. V. D. Linden, A. V. Goor","doi":"10.1109/TEST.1997.639686","DOIUrl":"https://doi.org/10.1109/TEST.1997.639686","url":null,"abstract":"TPG for synchronous sequential circuits has received wide attention over the last two decades, yet unlike for (full-scan) combinational circuits, for many sequential benchmark circuits 100% fault efficiency still cannot be reached. This illustrates the complexity of sequential circuit ATPG. The huge search space, which exists during sequential circuit TPG, is the main reason for this complexity. Powerful techniques and heuristics are required to cope with this search space. One way to reduce the search space is the detection of illegal states. These states cannot be justified with an initialization sequence. In this paper, we propose new techniques to find illegal states and to remove the over-specification of these states by searching common fractions in the list of illegal states. Experimental results demonstrate the importance of an as complete as possible illegal state list: Higher fault efficiencies are reached for the sequential ISCAS'89 circuits (1989) and industrial circuits, together with a large reduction of CPU time.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115718843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 256 Meg SDRAM BIST for disturb test application","authors":"T. Powell, D. Cline, F. Hii","doi":"10.1109/TEST.1997.639614","DOIUrl":"https://doi.org/10.1109/TEST.1997.639614","url":null,"abstract":"The Disturb Test Algorithms are targeted for row adjacent coupled defects that can be time elapsed dependent. A BIST design is described for application of these tests for testing 256 Meg SDRAM chips.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114692669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Stroud, M. Ding, S. Seshadri, R. Karri, I. Kim, Subhajit Roy, S. Wu
{"title":"A parameterized VHDL library for on-line testing","authors":"C. Stroud, M. Ding, S. Seshadri, R. Karri, I. Kim, Subhajit Roy, S. Wu","doi":"10.1109/TEST.1997.639654","DOIUrl":"https://doi.org/10.1109/TEST.1997.639654","url":null,"abstract":"We describe a library of parameterized VHDL models for various concurrent fault detection circuits and maintenance functions developed for simulation and synthesis of ASICs which support on-line testing and diagnostics in systems designed for high reliability and availability. Issues associated with the selection and modeling of the various online testing functions are also discussed.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124469118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An efficient scheme to diagnose scan chains","authors":"S. Narayanan, A. Das","doi":"10.1109/TEST.1997.639683","DOIUrl":"https://doi.org/10.1109/TEST.1997.639683","url":null,"abstract":"The scan chain needs to operate correctly to utilize the scan features in a design. The presence of defects in the chain can invalidate the test and debug methodology for a design. In this paper we present a novel strategy to efficiently diagnose a scan chain. The main idea is to add circuitry to a scan flop to enable its scan-out port to be either set or reset. Use of this circuitry requires no additional control signals, and has no impact on the timing of the design. Based on this set/reset feature, we then present a global strategy to efficiently incorporate it in a scan design. This strategy takes into account disparities in the defect probabilities and controllability/observability attributes of flops in a scan chain. An algorithm to optimally modify a subset of the flops to maximize diagnostic resolution is described. Experimental results on two devices highlight the advantages of the proposed strategy.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128406996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Toshiharu Asaka, Masaaki Yoshida, S. Bhattacharya, S. Dey
{"title":"H-SCAN+: a practical low-overhead RTL design-for-testability technique for industrial designs","authors":"Toshiharu Asaka, Masaaki Yoshida, S. Bhattacharya, S. Dey","doi":"10.1109/TEST.1997.639622","DOIUrl":"https://doi.org/10.1109/TEST.1997.639622","url":null,"abstract":"H-SCAN (1996) was presented as a low overhead design-for-testability strategy which is applicable to RT-level controller-data path circuits. However, from the view-point of practical use, there is a possibility that the area overhead of H-SCAN is larger than that of full-scan. Moreover, H-SCAN is unable to handle many features present in actual designs. In this paper, we propose a modified H-SCAN scheme, called \"H-SCAN+\", as an improved solution for actual designs. H-SCAN+ consists of several enhancements, including techniques to minimize scan design area overhead, handling of features present in actual designs, and techniques to significantly minimize the running time. We provide comprehensive results of applying H-SCAN+ to several actual RT-level designs.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127550952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Parker, J. McDermid, R. Browen, Kozo Nuriya, K. Hirayama, A. Matsuzawa
{"title":"Design, fabrication and use of mixed-signal IC testability structures","authors":"K. Parker, J. McDermid, R. Browen, Kozo Nuriya, K. Hirayama, A. Matsuzawa","doi":"10.1109/TEST.1997.639655","DOIUrl":"https://doi.org/10.1109/TEST.1997.639655","url":null,"abstract":"The goals of the studies of the MNABST-1 IC device were as follows: study the technical and economic feasibility of adding P1149.4 structures into mixed-signal devices; elicit design considerations at the silicon level and for silicon design software; study the interoperability of P1149.4 with 1149.1 interconnection test algorithms; study the efficacy of discrete component and network value measurements; establish limits on analog value measurements; and predict the capabilities of P1149.4 in the future. The results shows that we can emulate the capabilities of in-circuit test for most types of components currently tested this way. This will preserve the advantages of this well-known technology into the future when direct nodal access will no longer be the rule, but rather the exception.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130807134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Real time in-situ monitoring and characterization of production wafer probing process","authors":"Minh Quach, K. Harper","doi":"10.1109/TEST.1997.639694","DOIUrl":"https://doi.org/10.1109/TEST.1997.639694","url":null,"abstract":"This paper introduces a new technique that enables real-time monitoring and characterization of a production wafer probing process. Using this new technique, probing contact resistance data taken from production wafers has been correlated with wafer yield. Data are presented showing that production wafers are better suited for characterizing probing contact resistance than metalized setup wafers.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131003109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analog fault diagnosis for unpowered circuit boards","authors":"Jiun-Lang Huang, K. Cheng","doi":"10.1109/TEST.1997.639675","DOIUrl":"https://doi.org/10.1109/TEST.1997.639675","url":null,"abstract":"We present key portions of a method for automatic analog fault diagnosis for unpowered circuit boards. Our work consists of two major parts: (1) test point selection and (2) stimuli selection for diagnostic test generation. For test point selection, we propose an efficient graph-based algorithm achieving a desired level of diagnosibility. The stimuli selection algorithm uses a cost function derived from the sensitivity matrix to select test stimuli and thus avoids expensive circuit simulation. Experimental results of several industrial circuits show that our method is time efficient and promising in selecting high-quality stimuli.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131345728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design for primitive delay fault testability","authors":"Angela Krstic, K. Cheng, S. Chakradhar","doi":"10.1109/TEST.1997.639649","DOIUrl":"https://doi.org/10.1109/TEST.1997.639649","url":null,"abstract":"To guarantee the temporal correctness of a digital circuit a set of multiple path delay faults called primitive faults need to be tested. Primitive faults can contain one or more faulty paths. Existing techniques can identify and test primitive faults containing up to two or three paths. Identifying and testing primitive faults that consist of a larger number of paths is impractical for large designs. We propose a design for testability method that assures the temporal correctness of the circuit without the need to test all primitive faults in the circuit. In the test mode, only primitive faults that contain up to two paths can affect the circuit performance. Our methodology efficiently identifies a small set of potential locations for inserting control points to eliminate primitive faults with more than two paths. Addition of a single control point can lower the cardinality of several primitive faults. Our approach re-evaluates primitive delay fault testability of the circuit after insertion of every control point. After a few iterations only primitive faults with at most two paths can exist in the circuit in the test mode. Experimental results on several circuits are included to demonstrate our method.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"10 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122345555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}